HY27UG082G2M Hynix Semiconductor, HY27UG082G2M Datasheet

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Document Title 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 1) Add Errata Specification Relaxed value Specification Read(all) Except for Relaxed value ID Read 0.1 ID Read 2) Add note.4(table14) 3) Add application note(Power on/off Sequence ...

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Revision History Revision No. 1) Change Errata - Errata values (tWP & tWC) are changed 0.3 tCLH tCLS Before 5 After 5 1) Correct AC Timing Characristics Table - Errata value is eddited. - tADL(max) is changed to tADL(min) 2) ...

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Revision History Revision No. 1) Change 2Gb Package Type. - FBGA package is deleted. - WSOP package is changed to USOP package. - Figure & dimension are changed. 2) Correct PKG dimension (TSOP, USOP PKG) CP Before 0.050 After 0.100 ...

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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...

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... This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension. The HYNIX HY27(U/S)G(08/16)2G2M series is available TSOP1 USOP1 mm. 1.1 Product List PART NUMBER HY27SG082G2M HY27SG162G2M HY27UG082G2M HY27UG162G2M Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash ORIZATION VCC RANGE x8 1 ...

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IO15 - IO8 IO7 - IO0 CLE ALE CE# RE# WE# WP# RB# Vcc Vss NC PRE Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 ...

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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Figure 3. 48USOP1 Contactions, x8 and x16 Device Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 7 ...

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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE#). ...

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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 NOTE must be set to Low. IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A11 4th Cycle A19 5th Cycle A27 ...

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CLE ALE CE ( NOTE: 1. With ...

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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...

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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with five address cycles. In two consecutive read ...

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Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command (60h). Only address A18 to A28 (X8) or A17 to A27 (X16) is valid ...

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Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h, ...

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Cache Read Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page ...

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OTHER FEATURES 4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2.0V(3.3V device). WP# ...

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Parameter Symbol Valid Block Number Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage ...

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Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 4: Block Diagram 18 ...

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Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current I CC5 (CMOS) Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...

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Item Input / Output Capacitance Input Capacitance Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Program Time Dummy Busy Time for Cache Program Dummy Busy Time for Cache Read Dummy Busy Time for the Lock or Lock-tight Block Number of partial ...

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Parameter CLE Setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE# High hold time ALE to Data Loading time ...

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Pagae Block IO Program Erase 0 Pass / Fail Pass / Fail Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVICE IDENTIFIER BYTE 1st 2nd ...

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Description 1K Page Size 2K (Without Spare Area) Reserved Reserved Spare Area Size 8 (Byte / 512Byte) 16 Standard (50ns) Serial Access Time Fast 64K Block Size 128K (Without Spare Area) 256K Reserved X8 Organization X16 Not Used Table 17: ...

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Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 5: Command Latch Cycle Figure 6: Address Latch Cycle HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 24 ...

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Figure 8: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L) Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 7. Input Data Latch Cycle 25 ...

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Figure 10: Read1 Operation (Read One Page) Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 9: Status Read Cycle 26 ...

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Figure 11: Read1 Operation intercepted by CE# Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 27 ...

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Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 12 : Random Data output HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 28 ...

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Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 13: Page Program Operation HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 29 ...

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Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 14 : Random Data In HY27SG(08/16)2G2M Series 30 ...

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Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 15 : Copy Back Program HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 31 ...

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Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 16 : Cache Program 32 ...

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Figure 17: Block Erase Operation (Erase One Block) Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 18: Read ID Operation HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 33 ...

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Figure 19: start address at page start :after 1st latency uninterrupted data flow Figure 20: exit from cache read in 5us when device internally is reading Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND ...

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System Interface Using CE don’t care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So possible to connect NAND Flash to a microprocessor. The only function that was removed ...

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Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 23: Automatic Read at Power On Figure 24: Reset Operation HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 36 ...

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See the application Note 1. Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 25: Power On/Off Timing HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 37 ...

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Figure 26: Ready/Busy Pin electrical specifications Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 38 ...

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Figure 27: page programming within a block Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash 39 ...

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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...

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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 29~32) Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash ...

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Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit (256Mx8bit / 128Mx16bit) NAND Flash Figure 31: Enable Erasing Figure 32: Disable Erasing 42 ...

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APPENDIX : Extra Features 5.1 Automatic Page0 Read after Power Up The timing diagram related to this operation is shown in Fig. 23 Due to this functionality the CPU can directly download the boot loader from the first page ...

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Figure 33. 48-pin TSOP1 20mm, Package Outline Symbol alpha Table 20: 48-pin TSOP1 20mm, Package Mechanical Data Rev 0.7 / Nov. 2005 2Gbit (256Mx8bit / ...

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Figure 34. 48pin-USOP1 17mm, Package Outline Symbol alpha Table 20: 48pin-USOP1 17mm, Package Mechanical Data Rev 0.7 / Nov. 2005 HY27UG(08/16)2G2M Series HY27SG(08/16)2G2M Series 2Gbit ...

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MARKING INFORMATION ...

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Application Note 1. Power-on/off Sequence After power is on, the device starts an internal circuit initialization when the power supply voltage reaches a specific level. The device shows its internal initialization status with the Ready/Busy signal if initialization is on ...

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Automatic sleep mode for low power consumption The device provides the automatic sleep function for low power consumption. The device enters the automatic sleep mode by keeping CE# at VIH level for 10us without any additional command input, and ...