M62420FP Renesas Electronics Corporation., M62420FP Datasheet
M62420FP
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M62420FP Summary of contents
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... Electronic Volume with Tone by I Description M62420SP/FP/AFP is the tone and volume controller which is controlled by I application because of low noise and distortion. M62420AFP changes the slave address from M62420FP. Features TONE(Bass/Treble) control and 1 dB step volume control are enabled. Low noise and low distortion . ...
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M62420SP/ FP/ AFP Block diagram and Pin Configuration 20 19 VR2 ref ref VR1 ref 1 Rev.1.0, Sep.17.2003, page 1.8K VR4 VR6 SIMAMP2 136K ref TONE AMP2 6.5K ...
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M62420SP/ FP/ AFP Pin Description Pin No. Pin Name I/O Description 1 REF I Reference voltage terminal for analog 2 CH1 IN I Input terminal (ch1) 3 SIMIN1 I Pin for capacitor of simulated inductor 1 4 SIMOUT 1 O ...
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M62420SP/ FP/ AFP Thermal Derating Curves 1000 800 600 400 200 0 Recommended Operating Condition ( unless otherwise noted) Item Analog supply voltage Digital supply voltage H level input voltage (logic circuit) H level input voltage (logic ...
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M62420SP/ FP/ AFP Electrical Characteristics (DC 25°C, AVDD = 9 V, DVDD = 5 V and tone, bassboost = 0 dB unless otherwise noted ) (1) Supply voltage Item Analog supply current Digital supply current (2) I/O ...
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M62420SP/ FP/ AFP Function Explanation (1) Equivaration Circuit of Tone Control The resonance circuit is able to construct by using built-in amplifier for simulated inductor. (Shows the constant as follow (=1.8K ) ref FIG1. The circuit used ...
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M62420SP/ FP/ AFP BUS Input Data Format Input direction ( 1 ) slave S address starting term acknowledge bit ( 1 ) Slave address M62420SP / M62420AFP ...
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M62420SP/ FP/ AFP ( 3 ) -1: volume control The volume control is enabled at following condition. subA0 : subA1 : volume code D4 D3 ATT 0dB H H 2dB ...
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M62420SP/ FP/ AFP ( tone level control The tone level controlling is enabled at following condition. subA0 : 0 (both bits are 0) subA1 : 0 tone code D7 D6 12dB 10dB L ...
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M62420SP/ FP/ AFP DATA and CLOCK (IN (OUT) S start start This term is defined by SDA(in) falling edge at SCL H . stop This term is defined by SDA(in) ...
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M62420SP/ FP/ AFP BUS Line Timing Specification SDA HD:STA SU:DAT V IL SCL LOW S Parameter Min. input low voltage Max. input high voltage SCL clock frequency ...
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M62420SP/ FP/ AFP Level Diagram CH1 IN VOLAMP1 ref G1 0dB to -dB 136K ref CH2 IN Rev.1.0, Sep.17.2003, page 6.5K 1.8K same to CH1 -12dB to +12dB 6.5K G2 CH1 OUT TONEAMP1 CH2 OUT ...
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M62420SP/ FP/ AFP Logic Circuit Sub-address latch circuit Acknowledge generator Bi-direct SDA control SCL Rev.1.0, Sep.17.2003, page TONE AMP1 Level shifter Decoder, latch for tone control Slave address compare circuit Timing generator Shift register ANALOG BLOCK ref ...
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M62420SP/ FP/ AFP Application Example 2.2 F IN2 VCC 10K Reference circuit example 470 F 4.7K Reference 4.7K voltage IN1 2.2 10K Rev.1.0, Sep.17.2003, page ref 0.033 F 0.47 F 0.022 F 1. ...
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M62420SP/ FP/ AFP Package Dimensions Rev.1.0, Sep.17.2003, page ...
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M62420SP/ FP/ AFP c Rev.1.0, Sep.17.2003, page ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...