CXD2064Q Sony, CXD2064Q Datasheet
CXD2064Q
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CXD2064Q Summary of contents
Page 1
... Digital Comb Filter (NTSC/PAL) Description The CXD2064Q is an adaptive intra-field comb filter compatible with NTSC and PAL systems, and can provide high-precision Y/C separation with a single chip. Features • Adaptive intra-field Y/C separation • M-PAL and N-PAL supported • Vertical enhancer • Horizontal aperture correction • ...
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... Vertical enhancement circuit NTSC: 1H PAL : 2H DL Adaptive filter operation Logical operation Phase SW comparator 1 PLSL FIN CKSL – 2 – CXD2064Q DTR 23 PNR 22 VEH1 VEH2 21 20 VEH3 19 MOD1 MOD2 TEST IRF 11 ...
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... Normally fix to “Low”. NTSC/PAL/M-PAL/N-PAL mode setting. 25 NTPL2 I 26 NTPL1 — Digital power supply. (5.0V) DD Description MOD2 MOD1 L L Adaptive processing mode H L BPF separation mode H H Through mode NTPL2 NTPL1 – 3 – CXD2064Q NTSC PAL M-PAL N-PAL ...
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... VCO control voltage input. Connect to PLVS when not using the PLL. 44 VCV — 45 PLVD PLL analog power supply. (5.0V) — 46 CLVD Clamp D/A converter analog power supply. (5.0V) 47 CLPEN I Clamp circuit enable pin. Low: Clamp on, High: Clamp off. CLVS — Clamp D/A converter analog ground. 48 Description – 4 – CXD2064Q ...
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... I = 4mA 1.5mA OL 0.5 fmax = 50MHz sine wave 250k V = Vss – Vss 3.0 — – 5 – CXD2064Q = 0V –20 to +70°C) SS Applicable Typ. Max. Unit pins V 1 5.0 5.25 °C + — — 0. 500 ...
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... R = 200 , Ta = 25° 10MHz IRF Conditions Min. — 18 –0.8 –2.0 1.805 — — — 1Vp-p output Conditions Min. — – 6 – CXD2064Q = V = 0V) IN OUT Max. Unit 5V 25° 10MHz) DD Typ. Max. Unit 8 — bit — — ...
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... This circuit is valid in the adaptive processing and BPF separation modes noted above. • Using the internal PLL (clock selection method) PLL used PLL not used MOD2 (Pin 17) MOD1 (Pin 19 FIN (Pin 37) CKSL (Pin 38) fsc input H 2fsc input H 4fsc input L – 7 – CXD2064Q PLSL (Pin 39 L/H ...
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... Enhancement level OFF Max Enhancement level Limiter 0 –a a Limiter Pin settings VEH3 VEH2 VEH1 | a | (Pin 20) (Pin 21) (Pin 22 Large Small – 8 – CXD2064Q Luminance difference — ...
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... DAVS • Method of selecting the output resistor The CXD2064Q has a built-in current output type D/A converter. To obtain the output voltages, connect resistors to the AYO and ACO pins. The specs are as follows: output full-scale voltage V [mA]. Calculate the output resistance value using the relationship V times the output resistor to the reference current pin (IRF) ...
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... 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 200 C output Y output – 10 – CXD2064Q 0.1µ DTR PNR VEH1 VEH2 VEH3 L H ...
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... A/D converter: 3.5 clocks (“0.5” is for fetching the data at the fall of the clock.) Internal logic: 20 clocks D/A converter: 1 clock 2.60V (Reference top voltage typical value for internal A/D converter) 0.67V (Sync tip clamp level) 0.52V (Reference bottom voltage typical value for internal A/D converter) – 11 – CXD2064Q ...
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... 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 200 200 – 12 – CXD2064Q 0.1µ DTR PNR VEH1 VEH2 VEH3 L ...
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... 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 200 200 – 13 – CXD2064Q 0.1µ DTR PNR VEH1 VEH2 VEH3 L ...
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... 0.1µ 0.1µ 0.1µ 0.1µ 0.1µ 200 200 – 14 – CXD2064Q 0.1µ DTR PNR VEH1 VEH2 VEH3 L ...
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... SONY CODE EIAJ CODE JEDEC CODE 48PIN QFP (PLASTIC 0.15 0.3 – 0.1 0. 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-48P-L04 LEAD MATERIAL QFP048-P-1212 PACKAGE MASS – 15 – CXD2064Q + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.7g ...