MBM29PL160BD-75 Fujitsu, MBM29PL160BD-75 Datasheet

Page 1

... Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode • Low V write inhibit 2 Embedded Erase TM and Embedded Program 8/1M 16) BIT /MBM29PL160BD -75/-90 2 PROMs TM are trademarks of Advanced Micro Devices, Inc. To Top / Lineup / Index DS05-20872-1E -75/-90 (Continued) ...

Page 2

... Temporary sector unprotection Temporary sector unprotection with the software command • 5V tolerant (Data, Address, and Control Signals) • In accordance with CFI (Common Flash Memory Interface) PACKAGE Marking Side (FPT-48P-M19) 2 /MBM29PL160BD -75/-90 48-pin plastic TSOP (I) Marking Side 44-pin plastic SOP (FPT-44P-M16) To Top / Lineup / Index -75/-90 ...

Page 3

... The MBM29PL160TD/BD memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. To Top / Lineup / Index /MBM29PL160BD -75/-90 supply. 12 PROMs ...

Page 4

... Kbytes or 128 Kwords SA7 256 Kbytes or 128 Kwords SA8 256 Kbytes or 128 Kwords SA9 256 Kbytes or 128 Kwords SA10 256 Kbytes or 128 Kwords MBM29PL160BD Bottom Boot Sector Architecture 4 /MBM29PL160BD -75/- Address Range 000000H to 03FFFFH 040000H to 07FFFFH 080000H to 0BFFFFH 0C0000H to 0FFFFFH 100000H to 13FFFFH ...

Page 5

... Max. OE Access Time (ns) BLOCK DIAGRAM State WE Control BYTE Command Register CE OE Low V Detector /MBM29PL160BD -75/-90 MBM29PL160TD/160BD +0.6 V -75 –0 Erase Voltage Generator Program Voltage Generator Chip Enable Output Enable Logic Y-Decoder STB Timer for Address Program/Erase Latch ...

Page 6

... FPT-44P-M16 6 /MBM29PL160BD -75/-90 TSOP(I) BYTE 1 (Marking Side N. ...

Page 7

... MBM29PL160TD LOGIC SYMBOL BYTE To Top / Lineup / Index /MBM29PL160BD -75/-90 Table 1 MBM29PL160TD/BD Pin Configuration Pin Function Address Inputs Data Inputs/Outputs Chip Enable Output Enable OE Write Enable WE Selects 8-bit or 16-bit mode BYTE N ...

Page 8

... Notes: 1. Manufacturer and device codes may also be accessed via a command register write sequence. See Table 7. 2. Refer to the section on Sector Protection can 3.3 V ±10 /MBM29PL160BD -75/- ...

Page 9

... Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Output Disable If the OE input logic high level ( high-impedance state. /MBM29PL160BD -75/- time.) See Figure 5.1 for timing specifications. When reading ACC ...

Page 10

... IH In order to determine which sectors are write protected, A addresses; if the selected sector is protected, a logical ‘1’ will be output /MBM29PL160BD -75/-90 (11 12 address pin ...

Page 11

... 27H A (B) -1 MBM29PL160TD 0 (W) 2227H Device Code 45H A (B) -1 MBM29PL160BD 0 2245H (W) Sector Protection 01H Temporary Sector 01H Unprotection (B): Byte mode (W): Word mode /MBM29PL160BD -75/- Byte Byte Sector V ...

Page 12

... 180000H to 1BFFFFH 00000 - 11011 1C0000H to 1F7FFFH 1F8000H to 1F9FFFH 1FA000H to 1FBFFFH 1FC000H to 1FFFFFH Sector Address Tables (MBM29PL160BD Address Range 000000H to 003FFFH 004000H to 005FFFH ...

Page 13

... Once the mode is taken away using command register, all the previously protected sectors will be protected again. (See Figures 20.) /MBM29PL160BD -75/-90 and Addresses are latched on the falling edge ...

Page 14

... PD =Data to be programmed at location PA. Data is latched on the rising edge of WE. 5. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A Byte Mode: AAAH or 555H to addresses A 6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. 14 /MBM29PL160BD -75/-90 MBM29PL160TD/BD Standard Command Definitions Second Third Bus Bus ...

Page 15

... The operation is initiated by writing the Autoselect command sequence into the command register. Following the last command write, a read cycle from address XX00H retrieves the manufacture code of 04H. A read cycle from address XX01H for 16 (XX02H for 8) retrieves the device code (MBM29PL160TD = 27H and /MBM29PL160BD -75/-90 First Bus ...

Page 16

... MBM29PL160TD MBM29PL160BD = 45H for 8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for 16 mode). (See Tables 4.1 and 4.2.) All manufactures and device codes will exhibit odd parity with DQ The sector state (protection or unprotection) will be indicated by address XX02H for 16 (XX04H for 8). Scanning the sector addresses (A a logical “ ...

Page 17

... DQ suspended Program operation is detected by Data polling the regular Program operation. Note that DQ from any address. /MBM29PL160BD -75/-90 , Sector Erase Timer.) Any command other than Sector Erase 3 is “1” (See Write Operation Status section) ...

Page 18

... Please note that output data of upper byte ( operation necessary to write the read/reset command sequence into the register. 18 /MBM29PL160BD -75/-90 active current is required even “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate To Top / Lineup / Index -75/-90 ...

Page 19

... will be read on successive read attempts. 7 The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. See Figure 9 for the Data Polling timing specifications and diagrams. /MBM29PL160BD -75/-90 Table 9 Hardware Sequence Flags ...

Page 20

... second status check, the command may not have been accepted. See Table 9: Hardware Sequence Flags. 20 /MBM29PL160BD -75/-90 to toggle. In addition, an Erase Suspend/Resume command will 6 never stops toggling. Once the device has exceeded timing limits, the DQ ...

Page 21

... Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence. The device also incorporates several features to prevent inadvertent write cycles resulting form V and power-down transitions or system noise. /MBM29PL160BD -75/-90 to toggle during the Embedded Erase Algorithm. If the 2 ...

Page 22

... logical one. Power-up Write Inhibit Power-up of the devices with The internal state machine is automatically reset to read mode on power-up. 22 /MBM29PL160BD -75/-90 power-up and power-down, a write cycle is locked out for V CC < the command register is disabled and all internal program/erase circuits ...

Page 23

... Max. number of byte in 2Ah multi-byte write = 2 N 2Bh Number of Erase Block 2Ch Regions within device Erase Block Region 1 2Dh Information 2Eh 2Fh 30h /MBM29PL160BD -75/-90 Description 0051h Erase Block Region 2 Information 0052h 0059h 0002h 0000h Erase Block Region 3 ...

Page 24

... No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 24 /MBM29PL160BD -75/-90 , OE, and RESET (Note 1) ............ –0 +5 OE, and RESET pins are – ...

Page 25

... V –2.0 V Figure +2.0 V Figure 2 +13.5 V +13 +0 Note : This waveform is applied for A Figure 3 /MBM29PL160BD -75/- Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform OE, and RESET. 9 Maximum Positive Overshoot Waveform 2 ...

Page 26

... Embedded Erase or Embedded Program is in progress Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. Applicable for only sector protection. 5. The input voltage must be input after Vcc is valid. 26 /MBM29PL160BD -75/-90 Test Conditions ...

Page 27

... Input rise and fall times Input pulse levels: 0 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V Device Under Notes including jig capacitance (MBM29PL160TD/BD-75 100 pF including jig capacitance (MBM29PL160TD/BD-90) L /MBM29PL160BD -75/-90 Description Test Setup — — ...

Page 28

... BYTE Switching Low to Output HIGH-Z FLQZ — t BYTE Switching High to Output Active FHQV Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation. 28 /MBM29PL160BD -75/-90 Description Read Toggle and Data Polling Byte Word To Top / Lineup / Index -75/-90 MBM29PL160TD/BD Unit ...

Page 29

... MBM29PL160TD SWITCHING WAVEFORMS • Key to Switching Waveforms WAVEFORM Addresses OEH WE HIGH-Z Outputs Figure 5.1 /MBM29PL160BD -75/-90 INPUTS OUTPUTS Must Be Will Be Steady Steady May Will Be Change Change from from May Will Be Change Change from from “H” or “L”: ...

Page 30

... MBM29PL160TD Outputs Figure 5.2 30 /MBM29PL160BD -75/-90 Addresses Valid PRC t ACC OEH t PACC t OH HIGH Waveforms for Page Read Mode Operations To Top / Lineup / Index -75/- PACC ...

Page 31

... OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the 16 mode. (The addresses differ from 8 mode.) Figure 6 AC Waveforms for Alternate WE Controlled Program Operations /MBM29PL160BD -75/-90 Data Polling ...

Page 32

... OUT 5. Figure indicates last two bus cycles out of four bus cycle sequence. 6. These waveforms are for the 16 mode. (The addresses differ from 8 mode.) Figure 7 AC Waveforms for Alternate CE Controlled Program Operations 32 /MBM29PL160BD -75/-90 3rd Bus Cycle Data Polling 555H PA t ...

Page 33

... VCS the sector address for Sector Erase. Addresses = 555H (Word), AAAAH (Byte) for Chip Erase. 2. These waveforms are for the 16 mode. (The addresses differ from 8 mode.) Figure 8 AC Waveforms for Chip/Sector Erase Operations /MBM29PL160BD -75/-90 2AAH 555H 555H ...

Page 34

... AC Waveforms for Data Polling during Embedded Algorithm Operations OES OE DQ Data Stops toggling. (The device has completed the Embedded operation.) 6 Figure 10 AC Waveforms for Taggle Bit I during Embedded Algorithm Operations 34 /MBM29PL160BD -75/- OEH WHWH1 Output Flag ...

Page 35

... ELFH Figure 11 Timing Diagram for Word Mode Configuration CE BYTE t ELFL A-1 Figure 12 Timing Diagram for Byte Mode Configuration /MBM29PL160BD -75/- FHQV ...

Page 36

... MBM29PL160TD CE WE BYTE Figure 13 36 /MBM29PL160BD -75/-90 The falling edge of the last WE signal Input Valid t SET HOLD BYTE Timing Diagram for Write Operations To Top / Lineup / Index -75/-90 ...

Page 37

... CSP CE Data t VCS V CC SAX = Sector Address for initial sector SAY = Sector Address for next sector Note byte mode Figure 14 AC Waveforms for Sector Protection Timing Diagram /MBM29PL160BD -75/-90 t VLHT t WPP t VLHT t OESP To Top / Lineup / Index -75/-90 SAY 01H t OE ...

Page 38

... Suspend Erasing WE Erase Erase Suspend Toggle DQ and with OE Note read from the erase-suspended sector /MBM29PL160BD -75/-90 Enter Erase Suspend Program Erase Erase Suspend Read Suspend Read Program Figure Top / Lineup / Index -75/-90 Erase Resume Erase ...

Page 39

... MBM29PL160TD FLOW CHART Increment Address * : The sequence is applied for 16 mode. The addresses differ from 8 mode. Figure 16 /MBM29PL160BD -75/-90 Start Write Program Command Sequence (See Below) Data Polling Device No Verify Byte ? Yes No Last Address ? Yes Programming Completed Program Command Sequence* (Address/Command): 555H/AAH 2AAH/55H ...

Page 40

... MBM29PL160TD Chip Erase Command Sequence* (Address/Command): 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H * : The sequence is applied for 16 mode. The addresses differ from 8 mode. 40 /MBM29PL160BD -75/-90 Start Write Erase Command Sequece (See Below) Data Polling or Toggle Bit from Device No Data = FFH ? Yes Erasure Completed ...

Page 41

... MBM29PL160TD rechecked even “1” because Figure 18 /MBM29PL160BD -75/-90 VA =Address for programming =Any of the sector addresses Start within the sector being erased during sector erase or multiple erases operation. Read Byte =Any of the sector addresses ( within the sector not being Addr ...

Page 42

... MBM29PL160TD * : DQ is rechecked even changing to “1” /MBM29PL160BD -75/-90 Start Read ( Addr. = “H” or “L” Toggle 6 ? Yes Yes Read Byte ( Addr. = “H” or “L” Toggle Yes Fail Pass = “1” because DQ ...

Page 43

... MBM29PL160TD Increment PLSCNT No PLSCNT = 25? Yes Remove V from A ID Write Reset Command Device Failed * : byte mode Figure 20 /MBM29PL160BD -75/-90 Start Setup Sector Addr 19 16 PLSCNT = ...

Page 44

... MBM29PL160TD Notes: 1. All protected sectors are unprotected. 2. All previously protected sectors are protected once again. Figure 21 44 /MBM29PL160BD -75/-90 Start Temporary Unprotect Enable Command Write (Note 1) Perform Erase or Program Operations Temporary Unprotect Disable Command Write Temporary Sector Unprotection Completed (Note 2) Temporary Sector Unprotection Algorithm ...

Page 45

... MBM29PL160TD Increment Address * : The sequence is applied for 16 mode The addresses differ from 8 mode. Figure 22 Embedded Programming Algorithm for Fast Mode /MBM29PL160BD -75/-90 Start 555H/AAH 2AAH/55H 555H/20H XXXXH/A0H Program Address/Program Data Data Polling Device No Verify Byte? Yes No Last Address ? Yes Programming Completed XXXH/90H ...

Page 46

... Chip Programming Time Erase/Program Cycle PIN CAPACITANCE Parameter Parameter Description Symbol C Input Capacitance IN C Output Capacitance OUT C Control Pin Capacitance IN2 Note: Test conditions T = 25° 1.0 MHz A 46 /MBM29PL160BD -75/-90 Limits Min. Typ. Max. — 4.8 60 — 8.6 300 — 12.6 360 — 18 140 100,000 — ...

Page 47

... Fujitsu standard products are available in several packages. The order number is formed by a combination of: MBM29PL160 T D DEVICE NUMBER/DESCRIPTION MBM29PL160 16 Mega-bit (2M 3.0 V-only Read, Write, and Erase /MBM29PL160BD -75/-90 -80 PFTN PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout PFTR = 48-Pin Thin Small Outline Package ...

Page 48

... INDEX 24 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) 0.10(.004) 19.00±0.20 (.748±.008) 1996 FUJITSU LIMITED F48029S-2C /MBM29PL160BD -75/-90 *: Resin protruction. (Each side: 0.15(.006) Max) 48 Details of "A" part "A" 0.15(.006) 25 0.50(.0197) TYP 0.15±0.05 (.006±.002) 0.50±0.10 (.020±.004) ...

Page 49

... FUJITSU LIMITED F48030S-2C Top / Lineup / Index /MBM29PL160BD -75/-90 *: Resin protrusion. (Each side: 0.15(.006) Max) 48 Details of "A" part 0.15(.006) "A" 0.15(.006) 0.25(.010) 25 0.50±0.10 (.020±.004) 0.15± ...

Page 50

... MBM29PL160TD 44-pin plastic SOP (FPT-44P-M16) 28.45 44 INDEX LEAD No. 1 1.27(.050)TYP 0.10(.004) 26.67(1.050)REF 1998 FUJITSU LIMITED F44023S-4C /MBM29PL160BD -75/-90 +0.25 +.010 1.120 –0.20 –.008 23 13.00±0.10 16.00±0.20 (.512±.004) (.630±.008) 22 +0.10 +0.10 0.40 0.20 –0.05 –0.15 Ø0.13(.005) M +.004 (Stand off) .016 –.002 To Top / Lineup / Index -75/-90 2.35± ...

Page 51

... Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9907 FUJITSU LIMITED Printed in Japan To Top / Lineup / Index /MBM29PL160BD -75/-90 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...