HY5DV641622AT-33 Hynix Semiconductor, HY5DV641622AT-33 Datasheet
HY5DV641622AT-33
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HY5DV641622AT-33 Summary of contents
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... DDR SDRAM This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7/May. 02 HY5DV641622AT HY5DV641622AT 1 ...
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... Changed from 3.15V/3.30V/3.45V to 3.20V/3.30V/3.45V (min/typ/max) b) 300Mhz : Changed from 3.15V/3.30V/3.45V to 3.35V/3.45V/3.55V (min/typ/max) 6) Modified ‘Burst Read followed by Burst Write’ function - Burst Write command must be issued after ( ticks of clock from Burst Read command, not (CL + BL/2) ticks of clock at 300/275Mhz Rev. 0.7/May. 02 HY5DV641622AT 2 ...
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... Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) • Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe ORDERING INFORMATION Part No. Power Supply HY5DV641622AT-33 HY5DV641622AT- HY5DV641622AT-4 DDQ HY5DV641622AT-5 Rev. 0.7/May. 02 power supply • ...
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... NC 25 BA0 26 BA1 27 A10/ ROW and COLUMN ADDRESS TABLE Items Organization Row Address Column Address Bank Address Refresh HY5DV641622AT DQ15 64 V SSQ 63 DQ14 62 DQ13 61 V DDQ 60 DQ12 59 DQ11 58 V SSQ 57 DQ10 56 DQ9 55 ...
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... Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DV641622AT 5 ...
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... BA0, BA1 Rev. 0.7/May. 02 Write Data Register 2-bit Prefetch Unit 32 Bank 1Mx16/Bank0 Control 1Mx16/Bank1 1Mx16/Bank2 1Mx16/Bank3 Mode Row Register Decoder Column Decoder Column Address Counter DLL CLK Block Mode Register HY5DV641622AT DQ[0:15] LDQS, UDQS Data Strobe CLK_DLL Transmitter Data Strobe DS Receiver 6 ...
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... HY5DV641622AT A10/ CAS WE ADDR code code ...
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... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.7/May. 02 CKEn /CS, /RAS, /CAS, / HY5DV641622AT A10/ LDM UDM ADDR ...
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... OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DV641622AT Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DV641622AT Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL ...
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... OPCODE BA, CA, AP READ/READAP HY5DV641622AT Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL ...
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... H BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DV641622AT Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ...
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... HY5DV641622AT /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle ...
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... IDLE SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DV641622AT SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 14 ...
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... V in the following power up sequencing and attempt to maintain CKE at LVC- REF supply into any pin. Sequencing Voltage relationship to avoid latch-up After or with V DD After or with V DDQ After or with V DDQ HY5DV641622AT , then and finally DDQ . Except for TT < 0.3V DD < 0.3V DDQ < ...
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... CODE CODE tRP tMRD EMRS Set MRS Set Precharge All Reset DLL (with A8=H) *200 cycles of CK are required (for DLL locking) before any executable command can be applied. HY5DV641622AT NOP PRE AREF CODE CODE CODE 200 cycles of CK* tRP tRFC 2 or more ...
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... Yes CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved HY5DV641622AT Burst Length Burst Length Sequential Reserved Reserved Reserved ...
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... HY5DV641622AT Interleave ...
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... The HY5DV641622A supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength. Rev. 0.7/May. 02 HY5DV641622AT 19 ...
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... All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. Rev. 0.7/May RFU HY5DV641622AT DLL A0 DLL enable 0 Enable 1 Diable Output Driver Impedance Control Full Half RFU* Matched Impedance (Weak) 20 ...
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... DDQ 2% of the dc value. Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 10 = 0V) SS Max Unit 3.3 3.45 V 3.3 3.45 V 3.55 V 2.5 2.625 0.3 V DDQ - V - 0.15 V REF V + 0.04 V REF REF 0.51*V V DDQ DDQ HY5DV641622AT Unit sec Note ...
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... Unit 0. disabled 2.7V OUT OUT = 0V) SS Speed 150 130 120 20 = min 100 min CK 100 90 80 250 230 210 200 2 HY5DV641622AT Note -15.2mA +15.2mA OL Unit Note 5 100 190 1 ...
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... C, Voltage referenced to V Symbol Min 0.35 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ of the transmitting device and must track variations in the DC level of the same. DDQ o (TA Voltage referenced to VSS = 0V HY5DV641622AT = 0V) SS Max Unit 0.35 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit V x 0.5 V DDQ ...
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... AC t -1.0 0.5 -1.0 DQSCK - 0.4 - DQSQ t t HPmin HPmin QHS QHS t t CH/L CH min min t - 0.4 - QHS t 0 0 0.4 0.6 0.4 DQSH t 0.4 0.6 0.4 DQSL t 0.8 1.25 0.8 DQSS HY5DV641622AT 4 5 Max Min Max Min Max - 120K 36 120K 40 120K - 4 ...
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... Signal transitions through the DC region must be monotonic. Rev. 0.7/May Symbol Min Max Min t 0 0 0.9 1.1 0.9 RPRE t 0.4 0.6 0.4 RPST WPRES t 1.5 - 1.5 WPREH t 0.4 0.6 0.4 WPST MRD t 200 - 200 XSC t - 15.6 - REFI HY5DV641622AT 4 5 Max Min Max Min Max - 0 0.4 - 0.5 - 1.1 0.9 1.1 0.9 1.1 0.6 0.4 0.6 0.4 0 1.5 - 1.5 - 0.6 0.4 0.6 0.4 0 200 - 200 - 15.6 - 15.6 - 15.6 Unit Note ...
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... These values are guaranteed by design and are tested on a sample basis only. OUTPUT LOAD CIRCUIT Output R =25 S Rev. 0.7/May. 02 Pin CK, CK All other input-only pins DQ, DQS /2, V peak-to-peak = 0.2V O DDQ = Zo=50 C =30pF L HY5DV641622AT Symbol Min Max C 2.0 3 2.0 3 4.0 5 REF Unit ...
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... Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm. Rev. 0.7/May. 02 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) HY5DV641622AT Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) ...