CXD2453Q Sony, CXD2453Q Datasheet
CXD2453Q
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CXD2453Q Summary of contents
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... Timing Generator for LCD Panels For the availability of this product, please contact the sales office. Description The CXD2453Q is a timing signal generator for driving the LCX017AL and LCX023AL LCD panels. This chip outputs timing signals which support XGA signals (1024 768 dots) and S-XGA signals (1280 1024 dots) ...
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... HCK2 53 HST 55 SCLK 6 SDAT 7 SERIAL DATA I/F SCTL Master Clock (Sub – 2 – CXD2453Q 9 TST2 34 TST7 35 TST8 36 TST9 74 TST11 75 TST12 AUX V COUNTER 76 TST13 V POSITION 43 BLK COUNTER 19 SLFR 41 VCK V TIMING GENERATOR ...
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... Test pin (connect TST8 — Test pin (connect TST9 — Test pin (connect to V Description ) – 3 – CXD2453Q Input pin for open status — — — — — — — — — — — — — — — ...
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... O Auxiliary pulse output 70 ORACT O Auxiliary pulse output 71 V — GND SS 72 TST10 — Test pin (Not connected.) Description – 4 – CXD2453Q Input pin for open status — — — — — — — — — — — — — — — ...
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... DD V — 3.3V — — 4 < (min. value – 5 – CXD2453Q Input pin for open status — — — — — H — — H: Pull-up, L: Pull-down (Topr = –20 to +75° 0V) SS Max. Unit Applicable pins 3.6 — ...
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... HCK1, HCK2 HCK1, HCK2 50 50 50% 50% 50% 50 50% 50% – 6 – CXD2453Q = 3.3V ± 0.3V Min. Typ. Max. Unit — 10.5 — — — 10.5 — — = 90pF L = 50pF — — 30pF L = 90pF –5 — 90pF ...
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... V Symbol 50 (D15) 50% (D0) – 7 – CXD2453Q = 3.3V ± 0.3V 0V Min. Typ. Max — — 8T — — 4T — — 4T — — 4T — — 50% ...
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... Horizontal and vertical separate SYNC signals are input to the HSYNC (Pin 29) and VSYNC (Pin 28). The sync signals are compatible with both positive and negative polarity according to serial data settings. (Refer to the section on serial data interface for details regarding serial data.) The CXD2453Q supports signals which are shown in the following table. Horizontal scanning Effective dots ...
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... ORD10 ORD9 ORD4 ORD3 ORD2 ORD1 — — ORU10 ORU9 ORU4 ORU3 ORU2 ORU1 – 10 – CXD2453Q Settings D0 PLP8 PLL counter frequency division ratio PLP0 HP0 Screen horizontal position VP0 Screen vertical position SHP0 CXA2112R S/H control SLSX Operating mode, etc ...
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... Setting data SHPC SHPD SHP3 to SHP0 L L 1000 L L 1001 L L 1010 L L 1011 H H 1100 H H 1101 H H 1110 H H 1111 – 11 – CXD2453Q Output SHPA SHPB SHPC SHPD ...
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... The setting range is from "0" – 2). The same value cannot be set for IRD and IRU. Refer to the Timing Chart for the relationship between setting values and pulse positions. The default values are IRD10 through IRD0 = 00000000000, and IRU10 through IRU0 = 00010000000. SLXG SLSX – 12 – CXD2453Q ...
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... The timing by which a judgment of "no signal" is made and the free running cycle are as indicated below. Operating mode Free running detection timing (no signal period) and VST cycle during free running All modes Every 3H Every 4H Every 5H 128ck 8ck ORD = 000 /HEX 1600H – 13 – CXD2453Q 11 Every 1H ORU = 080 /HEX ...
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... PLL IC – 20 – CXD2453Q SN74HC244 (Vcc = 5.0V 0.1µ 10µ CLP2 40 10 CLP1 39 HRET TST9 36 35 ...
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... DETAIL A SONY CODE QFP-80P-L022 EIAJ CODE QFP080-P-1420 JEDEC CODE 80PIN QFP(PLASTIC 0.35 ± 0.10 0.16 M 0.30 0° to 10° DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 21 – CXD2453Q 3.35MAX 0.05MIN 0. EPOXY RESIN SOLDER PLATING 42 ALLOY 1.7g ...