K4D26323QG-GC33 Samsung, K4D26323QG-GC33 Datasheet
K4D26323QG-GC33
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K4D26323QG-GC33 Summary of contents
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... K4D26323QG-GC 128Mbit GDDR SDRAM INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...
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... Changed tWR of K4D26323QG-GC20 from 6tCK to 7tCK • Changed tWR of K4D26323QG-GC22 from 6tCK to 7tCK • Changed tWR of K4D26323QG-GC25 from 5tCK to 6tCK • Changed tWR of K4D26323QG-GC33 from 4tCK to 5tCK • Changed tWR of K4D26323QG-GC40 from 3tCK to 4tCK Revision 0.2 (April 20, 2004) • Changed tCK(max) of K4D26323QG-GC20 from 10ns to 5ns Revision 0.1 (April 16, 2004) • ...
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... Differential clock input ORDERING INFORMATION Part NO. K4D26323QG-GC25 K4D26323QG-GC2A K4D26323QG-GC33 * K4D26323QG-VC is the Lead Free package part number. GENERAL DESCRIPTION FOR 1M x 32Bit x 4 Bank DDR SDRAM The K4D26323QG is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG extremely high performance ...
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... K4D26323QG-GC PIN CONFIGURATION DQS0 DM0 VSSQ C DQ4 VDDQ NC D DQ6 DQ5 VSSQ E DQ7 VDDQ VDD F DQ17 DQ16 VDDQ DQ19 DQ18 VDDQ G H DQS2 DM2 NC J DQ21 DQ20 VDDQ DQ22 DQ23 VDDQ K CAS WE VDD L RAS BA0 N NOTE: 1. RFU1 is reserved for A12 2 ...
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... K4D26323QG-GC INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol CK, CK*1 Input CKE Input CS Input RAS Input CAS Input WE Input DQS ~ DQS Input/Output Input Input/Output Input Input Power Supply Power Supply DDQ SSQ V Power Supply ...
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... K4D26323QG-GC BLOCK DIAGRAM (1Mbit x 32I Bank) Bank Select CK,CK ADDR LCKE LRAS LCBR CK,CK CKE 32 Intput Buffer CK, CK Data Input Register Serial to parallel 64 1Mx32 1Mx32 1Mx32 1Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register CS RAS CAS ...
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... K4D26323QG-GC FUNCTIONAL DESCRIPTION • Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. ...
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... K4D26323QG-GC MODE REGISTER SET(MRS) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation ...
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... K4D26323QG-GC EXTENDED MODE REGISTER SET(EMRS) The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register) ...
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... VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. Output logic high voltage and low voltage is depend on output channel condition. 8. For K4D26323QG-G(V)C22, VDD&VDDQ=2.0V+0.1V Symbol V ...
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... K4D26323QG-GC DC CHARACTERISTICS Recommended operating conditions Unless Otherwise Noted, T Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby Current I CC2 in Power-down mode Precharge Standby Current I CC2 in Non Power-down mode Active Standby Current I CC3 power-down mode Active Standby Current I CC3 in Non Power-down mode ...
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... K4D26323QG-GC AC OPERATING TEST CONDITIONS Parameter Input reference voltage for CK(for single ended) CK and CK signal maximum peak swing CK signal minimum slew rate Input Levels Input timing measurement reference level Output timing measurement reference level Output load condition Note case of differential clocks(CK and CK ), input reference voltage for clock and CK’s crossing point. ...
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... K4D26323QG-GC AC CHARACTERISTICS (I) Parameter CL=3 CL=4 CK cycle time CL=5 CL=6 CK high level width CK low level width DQS out access time from CK Output access time from CK Data strobe edge to Dout edge Read preamble Read postamble CK to valid DQS-in DQS-In setup time DQS-in hold time DQS write postamble ...
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... K4D26323QG-GC Note The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case ...
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... K4D26323QG-GC AC CHARACTERISTICS (II) Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay for Read RAS to CAS delay for Write Row precharge time Last data in to Row precharge @Normal Precharge Last data in to Row precharge @Auto Pre- charge ...
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... K4D26323QG-GC AC CHARACTERISTICS (III) K4D26323QG-GC25 Frequency Cas Latency 400MHz ( 2.5ns ) 5 350MHz ( 2.86ns ) 5 300MHz ( 3.3ns ) 4 K4D26323QG-GC2A Frequency Cas Latency 350MHz ( 2.86ns ) 5 300MHz ( 3.3ns ) 4 K4D26323QG-GC33 Frequency Cas Latency 300MHz ( 3.3ns ) 4 tRC tRFC tRAS tRCDRD tRCDWR tRC tRFC tRAS ...
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... K4D26323QG-GC Simplified Timing( CK, CK BA[1:0] BAa BAa Ra A8/AP Ra ADDR (A0~A7 A9,A10) WE DQS DQ Da0 Da1 Da2 Da3 DM COMMAND ACTIVEA WRITEA tRCD tRAS Normal Write Burst (@ BL= BAa BAa Ra Ra PRECH ACTIVEA tRP tRC Multi Bank Interleaving Write Burst - 17 - 128M GDDR SDRAM ...
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... K4D26323QG-GC PACKAGE DIMENSIONS (144-Ball FBGA) 0.45 0.35 1.40 A1 INDEX MARK 12.0 <Top View> 0.8x11=8.8 0.10 Max 0 ± 0. ± 0.05 Max <Bottom View> 128M GDDR SDRAM 12.0 A1 INDEX MARK 0.8 0.40 0.40 Rev 1.2(Mar. 2005) Unit : mm ...