W27C010-70 Winbond, W27C010-70 Datasheet

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W27C010-70

Manufacturer Part Number
W27C010-70
Description
64K*8 bits high speed, low power electrically erasable EPROM
Manufacturer
Winbond
Datasheet

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GENERAL DESCRIPTION
The W27C010 is a high speed, low power Electrically Erasable and Programmable Read Only
Memory organized as 131072
provides an electrical chip erase function.
FEATURES
PIN CONFIGURATIONS
High speed access time:
70/150 nS (max.)
Read operating current: 30 mA (typ.)
Erase/Programming operating current:
1 mA (typ.)
Standby current: 5 A (typ.)
Single 5V power supply
Q0
A6
A5
A4
A3
A2
A1
A0
A7
GND
A12
Vpp
A15
A16
A1
Q0
Q2
A0
Q1
A7
A6
A5
A4
A3
A2
128K
5
8
9
10
11
12
13
6
7
1
4
Q
1
A
1
2
4 3 2 1 3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
1
5
1
5
32-pin PLCC
Q
2
A
1
6
1
6
G
N
D
V
p
p
1
7
Q
3
1
8
V
c
c
2
Q
4
8 ELECTRICALLY ERASABLE EPROM
/
P
G
M
1
9
Q
5
3
1
23
22
21
19
17
32
31
30
29
28
27
26
25
24
20
18
N
C
2
0
Q
6
3
0
28
25
24
22
21
29
27
26
23
8 bits that operates on a single 5 volt power supply. The W27C010
PGM
A9
A10
NC
A14
A13
A8
A11
OE
CE
Q7
Q6
Q5
Q4
Q3
Vcc
A10
A14
A13
OE
CE
Q7
A8
A9
A11
- 1 -
BLOCK DIAGRAM
PIN DESCRIPTION
+14V erase/+12V programming voltage
Fully static operation
All inputs and outputs directly TTL/CMOS
compatible
Three-state outputs
Available packages: 32-pin 600 mil DIP, 450
mil SOP and PLCC
SYMBOL
A0 A16
Q0 Q7
PGM
GND
V
V
OE
CE
NC
CC
PP
PGM
GND
A16
OE
V
CE
V
Publication Release Date: August 1997
A0
.
.
CC
PP
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Program Enable
Program/Erase Supply Voltage
Power Supply
Ground
No Connection
DECODER
CONTROL
DESCRIPTION
OUTPUT
BUFFER
ARRAY
CORE
W27C010
Q0
Q7
.
.
Revision A2

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W27C010-70 Summary of contents

Page 1

... ELECTRICALLY ERASABLE EPROM GENERAL DESCRIPTION The W27C010 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 131072 provides an electrical chip erase function. FEATURES High speed access time: 70/150 nS (max.) Read operating current (typ.) Erase/Programming operating current (typ ...

Page 2

... The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C010 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. ...

Page 3

... OE and PGM. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C010 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur ...

Page 4

... IL, IH, PGM = 2 -0 and removed simultaneously or after W27C010 RATING UNIT -55 to +125 C -65 to +125 -0.5 to +14.5 V -0.5 to +14.5 V LIMITS UNI T MIN. TYP. MAX. - ...

Page 5

... OUT OUT 1.5V/1. 100 pF +1.3V (IN914) 3.3K ohm 100 pF for 150 nS (Including Jig and Scope for 70 nS (Including Jig and Scope) Output Test Point Test Point 1.5V 1.5V Publication Release Date: August 1997 - 5 - W27C010 MAX. UNIT CONDITIONS = -0.4 mA/2 Revision A2 ...

Page 6

... V OUT 0. OUT MHz 2 -0 SYM. W27C010-70 MIN ACC and removed simultaneously or after W27C010 LIMITS MIN. TYP. MAX - ...

Page 7

... SYM. MIN. T 2.0 VPS PWP T 95 PWE T 2 2.0 OES T - OEV T 0 DFP 2.0 AHE T 2.0 CES and removed simultaneously or after V PP Publication Release Date: August 1997 - 7 - W27C010 LIMITS UNIT MIN. TYP. MAX -0.3 - 0.8 V 2 0. 11.5 12.0 12.5 V 11.75 12.0 12.25 V 4.5 5.0 5.5 V ...

Page 8

... A0 Stable Others AHC T DFP Data All One OUT VPS T T OES OE T OEV T PWE T CES - 8 - W27C010 Valid Output High Z Blank Check Read Verify Address Address Stable Stable T ACC D OUT D OUT ...

Page 9

... PGM V IL Program Program Verify Address Stable Address Stable T DFP Data In Stable OUT OUT CES T OES T OEV T PWP - 9 - W27C010 Read Verify Address Valid T ACC D OUT Publication Release Date: August 1997 Revision A2 ...

Page 10

... Address = First Location Vcc = 5V Vpp = 12V Program One 100 S Pulse Increment X Yes X = 25? No Fail Verify One Byte Pass No Last Address? Yes Vcc = 5V Vpp = 5V Compare Fail All Bytes to Original Data Pass Pass Device - 10 - W27C010 Verify Fail One Byte Pass Fail Device ...

Page 11

... Vpp = 14V A9 = 14V Chip Erase 100 mS Pulse Address = First Location Increment X Fail Erase Verify Pass No Last Address? Yes Vcc = 5V Vpp = 5V Compare Fail All Bytes to FFs (HEX) Pass Pass Device - 11 - W27C010 20? Yes Fail Device Publication Release Date: August 1997 Revision A2 ...

Page 12

... ORDERING INFORMATION PART NO. ACCESS TIME (nS) W27C010-70 70 W27C010-15 150 W27C010S-70 70 W27C010S-15 150 W27C010P-70 70 W27C010P-15 150 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...

Page 13

... A Base Plane Seating Plane Detail See Detail W27C010 Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.210 5.33 A 0.010 0. 0.150 0.155 0.160 3.81 3.94 4. 0.016 0.018 0.022 ...

Page 14

... Seating Plane W27C010 Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.140 3.56 A 0.020 0. 0.105 0.110 0.115 2.67 2.80 2. 0.026 0.032 0.66 0.81 1 0.028 0.71 b 0.018 ...

Page 15

... Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Winbond Microelectronics Corp. Kowloon, Hong Kong Winbond Systems Lab. TEL: 852-27513100 2727 N. First Street, San Jose, FAX: 852-27552064 CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Publication Release Date: August 1997 - 15 - W27C010 DESCRIPTION Revision A2 ...

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