UPD72870GM-8ED Renesas Electronics Corporation., UPD72870GM-8ED Datasheet
UPD72870GM-8ED
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UPD72870GM-8ED Summary of contents
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PRELIMINARY DATA SHEET IEEE1394 1-CHIP OHCI HOST CONTROLLER The PD72870, 72871 are the LSIs which integrated OHCI-Link and PHY function into a single chip. The PD72870, 72871 comply with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0 and ...
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BLOCK DIAGRAMS Top Block Diagram Serial ROM Interface PCI Bus/ Cardbus 2 Link PHY PHY Signal Preliminary Data Sheet S13925EJ2V0DS00 PD72870,72871 Cable Interface ...
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PHY Block Diagram PHY Control Signal (CMC,PC0-PC2) Link PHY/Link Interface Interface I/O Cable Power Status Remark Cable Port: Arbitration and Control State Machine Logic Receive Data Decoder and Generator Retimer Oscillator Transmit Data Encoder Transmit Generator Preliminary Data Sheet S13925EJ2V0DS00 ...
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Link Block Diagram PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap OPCI Internal Bus PCIS_CNT OPCIBUS_ARB ATDMA : Asynchronous Transmit DMA ATF : Asynchronous Transmit FIFO CIS : CIS Register CSR : Control and Status Registers IOREG ...
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PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) ( mm) PD72870GM-8ED L_V INTA ...
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LQFP (Fine pitch) ( mm) PD72871GM-8ED L_V INTA ...
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Plastic FBGA ( mm) PD72870 F1-FA2 PD72871 F1-FA2 Bottom View Remark : Pin connected on the FPBGA board ...
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PD72870 F1-FA2 RI0 RI1 AGND XO FIL0 P_AV 15 CPS AGND XI FIL1 DD P_AV 14 TpBias2 TpBias1 TpBias0 AGND DD P_AV 13 TpB2n TpB2p AGND AGND DD P_AV TpA2n TpA2p AGND 12 DD ...
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PD72871 F1-FA2 RI0 RI1 AGND XO FIL0 P_AV 15 CPS AGND XI FIL1 DD P_AV TPBias0 AGND DD P_AV AGND AGND DD P_AV NC NC AGND 12 DD ...
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PIN NAME AD0-AD31 : PCI Multiplexed Address and Data AGND : Analog GND CARD_ON : PCI/Card Select CBE0-CBE3 : Command/Byte Enables CIS_ON : CIS Register ON CLKRUN : PCICLK Running CMC : Configuration Manager Capable CPS : Cable Power Status ...
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PIN FUNCTIONS ................................................................................................................................... 13 1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 13 1.2 Cable Interface Signals: (15 pins) ................................................................................................ 14 1.3 PHY Signals: (9 pins)..................................................................................................................... 15 1.4 PHY Control Signals: (5 pins) ....................................................................................................... 15 1.5 PCI/Cardbus Select Signals: (2 pins) ...
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PHY FUNCTION .................................................................................................................................... 34 4.1 Cable Interface ............................................................................................................................... 34 4.1.1 Connections .......................................................................................................................................... 34 4.1.2 Cable Interface Circuit .......................................................................................................................... 35 4.1.3 CPS....................................................................................................................................................... 35 4.1.4 Unused Ports ........................................................................................................................................ 35 4.2 PLL and Crystal Oscillation Circuit.............................................................................................. 35 4.2.1 Crystal Oscillation Circuit...................................................................................................................... 35 ...
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PIN FUNCTIONS 1.1 PCI/Cardbus Interface Signals: (52 pins) Name I/O Pin No. LQFP FPBGA PAR I AD0-AD31 I/O 11-14, E1,E2, 16-19, F1,F2, 24-27, G1,G2, 29,30,32, H1,H2, 33,49,50, K1,K2, 52,53, L1,L2, 55-58, M1,M2, 61-64, N1,N2, 66-69 R5-R12, T5-T12 ...
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Name I/O Pin No. LQFP FPBGA PME CLKRUN I INTA PERR I SERR PRST PCLK 1.2 Cable Interface Signals: (15 pins) ...
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Name I/O Pin No. LQFP FPBGA PORTDIS I 105 H16 SUS_RESM I 106 G15 CPS I 123 A15 Note Please refer to 4.1.3 CPS. 1.3 PHY Signals: (9 pins) Name I/O Pin No. LQFP FPBGA TpBias0 O 128 C14 Note1 ...
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PCI/Cardbus Select Signals: (2 pins) Name I/O Pin No. LQFP FPBGA CARD_ON I 157 B3 CIS_ON I 156 A3 1.6 Serial ROM Interface Signals: (3 pins) Name I/O Pin No. LQFP FPBGA GROM_SDA I/O 153 A4 GROM_SCL O 154 ...
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IC pins) Name I/O Pin No. LQFP IC(H) I 75,99,100 IC(L) I 89,91,101,102,158, 159 IC(N) - 74,76-79,82-84, 86-88,92 1 Name I/O Pin No. LQFP PCI_V - 10,31,51,70 DD L_V - 1,20,40,46,59,72,81, DD 151 P_DV - ...
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PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 1 0000 0001 RHB IBR 0010 Extended (7) 0011 Max_speed 0100 Link_active Contender 0101 Resume_int ISBR 0110 0111 Page_select 1000 1001 1010 1011 ...
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Field Size R/W Reset value Extended 3 R 111 Total_ports 4 R 0011 or 0001 Max_speed 3 R 010 Delay 4 R 0010 Link_active 1 R/W 1 Contender 1 R/W See Description Jitter 3 R 010 Pwr_class 3 R/W See ...
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Field Size R/W Reset value Port_event 1 R/W Enab_accel 1 R/W Enab_multi 1 R/W Page_select 3 R/W 000 Port_select 4 R/W 0000 Reserved - R 000… 20 Table 2-1. Bit Field Description (3/3) 0 Set to 1 when the Int_Enable ...
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Port Status Page (Page 000 1000 AStat 1001 Negotiated_speed 1010 1011 1100 1101 1110 1111 Field Size R/W Reset value AStat BStat Child 1 R Connected 1 R Bias 1 R ...
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Vendor ID Page (Page 001 1000 1001 1010 1011 1100 1101 1110 1111 Field Size R/W Reset value Compliance_level 8 R 00000001 Vendor_ID 24 R 00004CH Product_ID 24 R Reserved - R 000… 22 Figure 2-3. Vendor ...
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CONFIGURATION REGISTERS 3.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) Device ID Status Class Code BIST Header Type Subsystem ID Expansion Rom Base Address Register 000000H Max_Lat Min_Gnt Power Management Capabilities Data PMCSR_BSE User Area ...
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Offset_00 Vendor ID Register This register identifies the manufacturer of the PD72870, 72871. The ID is assigned by the PCI_SIG committee. Bits R/W 15-0 R Constant value of 1033H. 3.1.2 Offset_02 DeviceID Register This register identifies the type of ...
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Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the PD72870, 72871. “Read” and “Write” are handled somewhat differently. Bits R/W 3-0 R Reserved Constant value of 0000 New ...
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Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the PD72870, 72871. Bits R/W 7-0 R Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions. ...
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Offset_10 Base Address 0 Register This register specifies the base memory address for accessing all the “Operation registers” (i.e. control, configuration, and status registers) of the PD72870, 72871, while the BIOS is expected to set this value during power-up ...
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Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the implementation of the 1394 OpenHCI specification. Bits R/W 7-0 R/W Default value of 00H. It specifies which input of the host system interrupt controller ...
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Offset_60 Cap_ID & Next_Item_Ptr Register The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the PD72870, 72871’s Capability List. ...
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Offset_64 Power Management Control/Status Register This is a 16-bit read-only register that provides control status information of the PD72870, 72871. Bits R/W 1,0 R/W PowerState Default value is undefined. This field is used both to determine the current power ...
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CardBus Mode Configuration Register ( CARD_ON=High ) Device ID Status Class Code BIST Header Type Base Address 1 (CardBus Status Reg) Base Address 2 (CardBus Status Reg) Subsystem ID Expansion Rom Base Address Register 000000H Max_Lat ...
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Offset_14/18 Base_Address_1/2 Register (CardBus Status Registers) Bits R/W 7-0 R Constant value of 00. 31-8 R/W - (1) Function Event Register (FER) ( Base Address Bits R Write Protect (No Use). ...
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Function Reset Status Register (FRSR) ( Base Address Bits R Write Protect (No Use). Read only as ‘0’ Ready Status (No Use). Read only as ‘0’ Battery ...
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PHY FUNCTION 4.1 Cable Interface 4.1.1 Connections Connection Detection Current Connection Detection Comparator + - Driver Receiver + - Arbitration Comparators + - + - ...
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Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the ...
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SERIAL ROM INTERFACE The PD72870, 72871 provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the PCI/Cardbus Mode Configuration registers from a serial EEPROM. 5.1 Serial EEPROM Register Register Address Base address + 0x930 ...
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W_GUIDHi register (Base address + 0x938) 31 Field Bits R/W Default value W_GUIDHi 31-0 R/W Undefined (4) W_GUIDLo register (Base address + 0x93C) 31 Field Bits R/W Default value W_GUIDLo 31-0 R/W Undefined (5) Parameters Write register (Base address ...
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W_GENERAL register (Base address + 0x950 - 0x95C) 31 W_GENERAL_0 (Base address + 0x950) - W_GENERAL_3 (Base address + 0x95C) Field Bits R/W Default value W_GENERAL_0 - 31-0 R/W Undefined W_GENERAL_3 (7) W_PHYS register (Base address + 0x960) 31 ...
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Table 5-1. Serial EEPROM Memory Map Byte address ...
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Load Control GROM_EN CARD_ON CIS_ON loading W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - W_GENERAL_3, W_programPhyEnable, W_aPhyEnhanceEnable are loaded All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_GENERAL_0 - ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Operating temperature Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ...
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DC Characteristics ( Parameter High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current PCI interface High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current ...
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Remarks 1. Digital core runs at 3 PCI Interface can run 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI. 3. All other I/Os are 3.3 V driving, and 5 V tolerant. ...
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APPLICATION CIRCUIT EXAMPLE 0 0.1 F Digital GND ...
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PACKAGE DRAWINGS 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) 120 121 160 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC FBGA (14 x 14mm 0.1 0.3 13.4 + 0.1 9 1.0 1 R0.3 MAX 0. 0.10 S ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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EEPROM is a trademark of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that ...