UPD72870AF1-FA2 Renesas Electronics Corporation., UPD72870AF1-FA2 Datasheet
UPD72870AF1-FA2
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UPD72870AF1-FA2 Summary of contents
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PRELIMINARY DATA SHEET IEEE1394 1-CHIP OHCI HOST CONTROLLER The PD72870A is the LSI which integrated OHCI-Link and PHY function into a single chip. The PD72870A complies with the P1394a draft 2.0 specifications and the OpenHCI IEEE1394 1.0, and works up ...
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Firewarden™ ROADMAP IEEE1394-1995 Core Development OHCI Link PD72860 Link Core 1997 1998 2 Firewarden Series OHCI Link PD72862 1 Chip OHCI+PHY OHCI Link PD72870A PD72861 1 Chip OHCI+PHY PD72870 1999 Preliminary Data Sheet S14653EJ1V0DS00 PD72870A PC Application 800M/1.6G P1394.b Link ...
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BLOCK DIAGRAMS Top Block Diagram Serial ROM Interface PCI Bus/ Cardbus Link PHY PHY Signal Preliminary Data Sheet S14653EJ1V0DS00 PD72870A Cable Interface 3 ...
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PHY Block Diagram PHY Control Signal (CMC,PC0-PC2) Link PHY/Link Interface Interface I/O Cable Power Status Remark Cable Port: 4 Arbitration and Control State Machine Logic Receive Data Decoder and Generator Retimer Oscillator Transmit Data Encoder Generator Preliminary Data Sheet S14653EJ1V0DS00 ...
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Link Block Diagram PCI Controller Interface (Master, Parity Check & Generator) Byte Buf Swap OPCI Internal Bus PCIS_CNT OPCIBUS_ARB ATDMA : Asynchronous Transmit DMA ATF : Asynchronous Transmit FIFO CIS : CIS Register CSR : Control and Status Registers IOREG ...
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PIN CONFIGURATION • 160-pin plastic LQFP (Fine pitch) (24 x 24) PD72870AGM-8ED L_V INTA ...
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FBGA (14 x 14) PD72870AF1-FA2 Bottom View Remark : Pin connected on the FBGA board ...
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PD72870AF1-FA2 RI0 RI1 AGND XO FIL0 P_RESETB P_AV P_AV CPS AGND XI FIL1 15 DD P_AV 14 TpBias2 TpBias1 TpBias0 AGND DGND DD P_AV 13 TpB2n TpB2p AGND AGND DGND DD P_AV TpA2n TpA2p ...
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PIN NAME AD0-AD31 : PCI Multiplexed Address and Data AGND : Analog GND CARD_ON : PCI/Card Select CBE0-CBE3 : Command/Byte Enables CIS_ON : CIS Register ON CLKRUN : PCICLK Running CMC : Configuration Manager Capable CPS : Cable Power Status ...
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PIN FUNCTIONS ................................................................................................................................... 12 1.1 PCI/Cardbus Interface Signals: (52 pins)..................................................................................... 12 1.2 Cable Interface Signals: (15 pins) ................................................................................................ 13 1.3 PHY Signals: (9 pins)..................................................................................................................... 14 1.4 PHY Control Signals: (5 pins) ....................................................................................................... 14 1.5 PCI/Cardbus Select Signals: (2 pins) ...
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PHY FUNCTION .................................................................................................................................... 33 4.1 Cable Interface ............................................................................................................................... 33 4.1.1 Connections .......................................................................................................................................... 33 4.1.2 Cable Interface Circuit .......................................................................................................................... 34 4.1.3 CPS....................................................................................................................................................... 34 4.1.4 Unused Ports ........................................................................................................................................ 34 4.2 Suspend/Resume........................................................................................................................... 35 4.2.1 Suspend/Resume On Mode (SUS_RESM = 1)..................................................................................... 35 4.2.2 ...
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PIN FUNCTIONS 1.1 PCI/Cardbus Interface Signals: (52 pins) Name I/O Pin No. LQFP FBGA PAR I AD0-AD31 I/O 11-14, E1,E2, 16-19, F1,F2, 24-27, G1,G2, 29,30,32, H1,H2, 33,49,50, K1,K2, 52,53, L1,L2, 55-58, M1,M2, 61-64, N1,N2, 66-69 R5-R12, T5-T12 ...
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Name I/O Pin No. LQFP FBGA DEVSEL I STOP I PME CLKRUN I INTA PERR I SERR PRST PCLK I ...
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Name I/O Pin No. LQFP FBGA PORTDIS I 105 H16 SUS_RESM I 106 G15 CPS I 123 A15 Note Please refer to 4.1.3 CPS. 1.3 PHY Signals: (9 pins) Name I/O Pin No. LQFP FBGA TpBias0 O 128 C14 TpBias1 ...
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PCI/Cardbus Select Signals: (2 pins) Name I/O Pin No. LQFP FBGA CARD_ON I 157 B3 CIS_ON I 156 A3 1.6 Serial ROM Interface Signals: (3 pins) Name I/O Pin No. LQFP FBGA GROM_SDA I/O 153 A4 GROM_SCL O 154 ...
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V DD Name I/O Pin No. LQFP PCI_V - 10,31,51,70 DD L_V - 1,20,40,46,59,72,81, DD 151 P_DV - 97,103,107,108,149 DD P_AV - 111 DD - 116 - 120,125 - 146-148 1.10 GND Name I/O Pin No. LQFP DGND - ...
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PHY REGISTERS 2.1 Complete Structure for PHY Registers Figure 2-1. Complete Structure of PHY Registers 0 1 0000 0001 RHB IBR 0010 Extended (7) 0011 Max_speed 0100 Link_active Contender 0101 Resume_int ISBR 0110 0111 Page_select 1000 1001 1010 1011 ...
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Field Size R/W Reset value Extended 3 R 111 Total_ports 4 R 0011 Max_speed 3 R 010 Delay 4 R 0010 Link_active 1 R/W Contender 1 R/W See Description Jitter 3 R 010 Pwr_class 3 R/W See Description Resume_int 1 ...
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Field Size R/W Reset value Port_event 1 R/W 0 Enab_accel 1 R/W 0 Enab_multi 1 R/W 0 Page_select 3 R/W 000 Port_select 4 R/W 0000 Reserved - R 000… Table 2-1. Bit Field Description (3/3) Description Set to 1 when ...
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Port Status Page (Page 000 1000 AStat 1001 Negotiated_speed 1010 1011 1100 1101 1110 1111 Field Size R/W Reset value AStat 2 R BStat 2 R Child 1 R Connected 1 R Bias 1 R Disabled 1 ...
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Vendor ID Page (Page 001 1000 1001 1010 1011 1100 1101 1110 1111 Field Size R/W Reset value Compliance_level 8 R 00000001 Vendor_ID 24 R 00004CH Product_ID 24 R Reserved - R 000… Figure 2-3. Vendor ID ...
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CONFIGURATION REGISTERS 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low Device ID Status Class Code BIST Header Type Subsystem ID Expansion Rom Base Address Register 000000H Max_Lat Min_Gnt Power Management Capabilities Data PMCSR_BSE User Area ...
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Offset_00 Vendor ID Register This register identifies the manufacturer of the PD72870A. The ID is assigned by the PCI_SIG committee. Bits R/W 15-0 R Constant value of 1033H. 3.1.2 Offset_02 Device ID Register This register identifies the type of ...
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Offset_06 Status Register This register tracks the status information of PCI-bus related events which are relevant to the PD72870A. “Read” and “Write” are handled somewhat differently. Bits R/W 3-0 R Reserved Constant value of 0000 New capabilities ...
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Offset_08 Revision ID Register This register specifies a revision number assigned by NEC Corporation for the PD72870A. Bits R/W 7-0 R Default value of 02H. It specifies the silicon revision. It will be incremented for subsequent silicon revisions. 3.1.6 ...
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Offset_10 Base Address 0 Register This register specifies the base memory address for accessing all the “Operation registers” (i.e. control, configuration, and status registers) of the PD72870A, while the BIOS is expected to set this value during power-up reset. ...
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Offset_3C Interrupt Line Register This register provides the interrupt line routing information specific to the PD72870A, the NEC’s implementation of the 1394 OpenHCI specification. Bits R/W 7-0 R/W Default value of 00H. It specifies which input of the host ...
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Offset_60 Cap_ID & Next_Item_Ptr Register The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the Next_Item_Ptr describes the location of the next item in the PD72870A’s Capability List. Bits ...
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Offset_64 Power Management Control/Status Register This is a 16-bit read-only register that provides control status information of the PD72870A. Bits R/W 1,0 R/W PowerState Default value is undefined. This field is used both to determine the current power state ...
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CardBus Mode Configuration Register (CARD_ON = High Device ID Status Class Code BIST Header Type Base Address 1 (CardBus Status Reg) Base Address 2 (CardBus Status Reg) Subsystem ID Expansion Rom Base Address Register 000000H Max_Lat ...
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Offset_14/18 Base_Address_1/2 Register (Cardbus Status Registers) Bits R/W 7-0 R Constant value of 00. 31-8 R/W - (1) Function Event Register (FER) ( Base Address Bits R Write Protect (No Use). ...
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Function Reset Status Register (FRSR) ( Base Address Bits R Write Protect (No Use). Read only as ‘0’ Ready Status (No Use). Read only as ‘0’ Battery ...
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PHY FUNCTION 4.1 Cable Interface 4.1.1 Connections Connection Detection Current Connection Detection Comparator + - Driver Receiver + - Arbitration Comparators + - + - ...
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Cable Interface Circuit Each port is configured with two twisted-pairs of TpA and TpB. TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables. During transmission to the IEEE1394 bus, the ...
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Suspend/Resume 4.2.1 Suspend/Resume On Mode (SUS_RESM = 1) There are two ways of transition from the active status to the suspended status. One is when the receipt of a remote command packet that sets the initiate suspend command. After ...
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PLL and Crystal Oscillation Circuit 4.3.1 Crystal Oscillation Circuit To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor and a crystal of 50 ppm. 4.3.2 PLL The crystal oscillator multiplies the ...
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SERIAL ROM INTERFACE The PD72870A provides a serial ROM interface to initialize the 1394 Global Unique ID Register and the PCI/Cardbus Mode Configuration registers from a serial EEPROM. The table 5-1 shows the serial EEPROM memory map required for ...
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W_GUIDHi register (Base address + 0x938) 31 Field Bits R/W Default value W_GUIDHi 31-0 R/W Undefined (4) W_GUIDLo register (Base address + 0x93C) 31 Field Bits R/W Default value W_GUIDLo 31-0 R/W Undefined (5) Parameters Write register (Base address ...
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W_LAT register (Base address + 0x950) 31 Field Bits R/W Default value - 31-8 - W_LAT 7-3 R/W 00000 - 2-0 - (7) W_GENERAL register (Base address + 0x954 - 0x95C) 31 W_GENERAL_0 (Base address + 0x954) - W_GENERAL_2 ...
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W_CIS register (Base address + 0x980 - 0x984) 31 W_CIS_EVEN (Base address + 0x980) - W_CIS_ODD (Base address + 0x984) Field Bits R/W Default value W_CIS_EVEN - 31-0 R/W Undefined W_CIS_ODD 40 Description CIS Area value. The value is ...
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Table 5-1. Serial EEPROM Memory Map Byte address ...
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Load Control GROM_EN CARD_ON CIS_ON loading W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_LAT, W_GENERAL_0 - W_GENERAL_2, W_programPhyEnable, W_aPhyEnhanceEnable are loaded All parameters (W_SUBSYSID, W_SUBVNDID, W_MAXLAT, W_MINGNT, W_MAX_REC, W_GUIDHi/Lo, W_LAT, ...
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Write W_CIS_0, W_CIS_1 register. • Write PAGE_S = 100 and PAR_W = 1 on Parameters Write register. • Wait over 30 ms for serial EEPROM access time. : • Write W_CIS_30, W_CIS_31 register. • Write PAGE_S = 100 ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute ...
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DC Characteristics ( Parameter High-level input voltage Low-level input voltage High-level output current Low-level output current Input leakage current Supply current PCI interface High-level input voltage Low-level input voltage High-level output current Low-level output current Input ...
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Remarks 1. Digital core runs at 3 PCI Interface can run 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI. 3. All other I/Os are 3.3 V driving, and 5 V tolerant. ...
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APPLICATION CIRCUIT EXAMPLE 0 0.1 F Digital GND ...
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PACKAGE DRAWINGS 160-PIN PLASTIC LQFP (FINE PITCH) (24x24) 120 121 160 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition ...
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PLASTIC FBGA (14x14 INDEX MARK 4-R0.3 MAX. 4-C1 192 Preliminary ...
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Preliminary Data Sheet S14653EJ1V0DS00 PD72870A ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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EEPROM and Firewarden are trademarks of NEC Corporation. The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from ...