MCM69P737TQ4R Freescale Semiconductor, Inc, MCM69P737TQ4R Datasheet

MCM69P737TQ4R

Manufacturer Part Number

MCM69P737TQ4R

Description

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCM69P737TQ4R.pdf (20 pages)

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

128K x 36 Bit Pipelined

BurstRAM Synchronous

Fast Static RAM

a burstable, high performance, secondary cache for the PowerPC

high performance microprocessors. It is organized as 128K words of 36 bits

each. This device integrates input registers, an output register, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

control with the use of an external clock (K).

enable (G) and linear burst order (LBO) are clock (K) controlled through positive–

edge–triggered noninverting registers.

addresses can be generated internally by the MCM69P737 (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO) and

controlled by the burst address advance (ADV) input pin.

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

nous write enable (SW) are provided to allow writes to either individual bytes or

to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls

DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte

writes SBx are asserted with SW. All bytes are written if either SGW is asserted

or if all SBx and SW are asserted.

edge–triggered output register and then released to the output buffers at the next

rising edge of clock (K).

operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC stan-

dard JESD8–5 compatible.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

REV 6

1/20/98

MOTOROLA FAST SRAM

The MCM69P737 is a 4M bit synchronous fast static RAM designed to provide

Addresses (SA), data inputs (DQx), and all control signals except output

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst

Write cycles are internally self–timed and are initiated by the rising edge of the

Synchronous byte write (SBx), synchronous global write (SGW), and synchro-

For read cycles, pipelined SRAMs output data is temporarily stored by an

The MCM69P737 operates from a 3.3 V core power supply and all outputs

Motorola, Inc. 1998

MCM69P737–3.5: 3.5 ns Access/6 ns Cycle (166 MHz)

MCM69P737–3.8: 3.8 ns Access/6.7 ns Cycle (150 MHz)

MCM69P737–4: 4 ns Access/7.5 ns Cycle (133 MHz)

3.3 V + 10%, – 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

ADSP, ADSC, and ADV Burst Control Pins

Selectable Burst Sequencing Order (Linear/Interleaved)

Single–Cycle Deselect Timing

Internally Self–Timed Write Cycle

Byte Write and Global Write Control

PB1 Version 2.0 Compatible

JEDEC Standard 119–Pin PBGA and 100–Pin TQFP Packages

and other

MCM69P737

CASE 983A–01

Order this document

TQ PACKAGE

ZP PACKAGE

CASE 999–02

by MCM69P737/D

PBGA

TQFP

MCM69P737

Related parts for MCM69P737TQ4R

MCM69P737TQ4R Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P737 bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC high performance microprocessors. It ...

Page 2

LBO ADV K ADSC ADSP SA SA1 SA0 SGW SW SBa SBb SBc SBd SE1 SE2 SE3 G MCM69P737 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 17 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c ...

Page 3

A V DDQ SA SA ADSP SE2 SA ADSC SA SE3 DQc DQc DQb E DQc ...

Page 4

PBGA PIN DESCRIPTIONS Pin Locations (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, ...

Page 5

TQFP PIN DESCRIPTIONS Pin Locations (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79 12, 13 (d) 18, ...

Page 6

TRUTH TABLE (See Notes 1 Through 5) Address Used Next Cycle SE1 Deselect None 1 Deselect None 0 Deselect None 0 Deselect None X Deselect None X Begin Read External 0 Begin Read External 0 Continue Read Next X Continue ...

Page 7

ABSOLUTE MAXIMUM RATINGS (See Note 1) Rating Symbol Power Supply Voltage V DD I/O Supply Voltage V DDQ Input Voltage Relative for out Any Pin Except V DD Input Voltage (Three–State I/O) V ...

Page 8

DC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O Supply Parameter Supply Voltage I/O Supply Voltage Input Low Voltage ...

Page 9

DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Input Leakage Current ( Output Leakage Current ( DDQ ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes V DD ...

Page 10

AC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 10%, – 5 Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . ...

Page 11

OUTPUT Figure 3. Lumped Capacitive Load and Typical Derating Curve INPUT WAVEFORM OUTPUT WAVEFORM NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.5 to 2.0 V unloaded. 3. Fall time is ...

Page 12

PULL–UP VOLTAGE (V) I (mA) MIN I (mA) MAX – 0.5 – – 38 0.8 – 38 1.25 – 26 1.5 – 20 2.3 0 2.7 0 2.9 0 PULL–UP VOLTAGE (V) I (mA) MIN I (mA) MAX ...

Page 13

MOTOROLA FAST SRAM MCM69P737 13 ...

Page 14

STOP CLOCK OPERATION In the stop clock mode of operation, the SRAM will hold all state and data values even though the clock is not running (full static operation). The SRAM design allows the clock to start with ADSP and ...

Page 15

K ADSC ADDRESS A1 WRITE ADV DATA IN D(A1) DQx ADSC (INITIATES BURST WRITE) NOTE: While the clock is stopped, DATA IN must be fixed in a high ( low ( state to reduce the ...

Page 16

STOP CLOCK WITH DESELECT OPERATION TIMING K ADSC SE1 DATA IN DQx DATA CONTINUE BURST READ (DESELECTED) NOTE: While the clock is stopped, DATA IN must be fixed in a high ( low ( state ...

Page 17

... MCM 69P737 Blank = Trays Tape and Reel Speed (3.5 = 3.5 ns, 3.8 = 3.8 ns ns) Package (ZP = PBGA TQFP) MCM69P737ZP3.8 MCM69P737ZP3.5R MCM69P737ZP3.8R MCM69P737TQ3.5 MCM69P737TQ3.8 MCM69P737TQ3.5R MCM69P737TQ3. ADSP ADSC ADV SE1 SE2 LBO D(E) D(F) D(G) D(H) WRITES MCM69P737ZP4 MCM69P737ZP4R MCM69P737TQ4 MCM69P737TQ4R MCM69P737 17 ...

Page 18

TOP VIEW SIDE VIEW A1 MCM69P737 18 PACKAGE DIMENSIONS ZP PACKAGE BUMP PBGA CASE 999–02 b 119X 0 0. ...

Page 19

H A– –A– 100 1 D1 TIPS 0.20 (0.008) C A–B A –H– –C– SEATING PLANE 0.05 (0.002 VIEW AB MOTOROLA FAST SRAM TQ PACKAGE TQFP ...

Page 20

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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