MC88921 Freescale Semiconductor, Inc, MC88921 Datasheet
MC88921
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MC88921 Summary of contents
Page 1
... The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple locations on a board. The PLL also allows the MC88921 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency ...
Page 2
... MC88921 Power–Down Mode Functionality The MC88921 has a special feature designed in to allow the processor clock inputs to be reset for total processor power–down, and then to return to phase–locked operation very quickly when the processor is powered–up again. The MR pin resets outputs 2X_Q, Q0 and Q1 only leaving the other outputs operational for other system activity ...
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... Guaranteed Limits 4.75 2.0 5.25 2.0 4.75 0.8 5.25 0.8 4.75 4.01 5.25 4.51 4.75 0.44 5.25 0.44 5.25 1.0 2.0 2 5.25 5.25 88 5.25 –88 5.25 750 Parameter 3 MC88921 Limits Unit 5.0 10 > 1500 V Unit Condition V V OUT = 0. – 0. OUT = 0. – 0. –36mA –36mA +36mA +36mA µ ...
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... Maximum Operating Frequency, Q0–Q3 Outputs 1. Maximum Operating Frequency is guaranteed with the 88921 in a phase–locked condition, and all outputs loaded at 50pF. MOTOROLA RC1 D CH VCO PUMP Figure 1. MC88921 Logic Block Diagram 5%) Parameter 4 LOCK 2X_Q “ ...
Page 5
... Clock Cycles ns (Q Frequency) 5 — MC88921 Condition t RISE – 0.8V to 2.0V t FALL – 2.0V to 0.8V t RISE – 0.8V to 2.0V t FALL – 2.0V to 0.8V 50Ω Load Terminated (See Application Note 3) 50Ω Load Terminated (See Application Note 3) With 1MΩ From RC1 ...
Page 6
... However, to correctly predict the skew from a given output on one part to any other output on one or more other parts, the distribution of each output in relation to the SYNC input must be known. This distribution for the MC88921 is provided in Table 1. TABLE 1. Distribution of Each Output versus SYNC Output ...
Page 7
... Output Figure 5. Output/Input Switching Waveforms and Timing Relationships 1. The MC88921 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the crossing point of the appropriate output edges. All skews are specified as ‘ ...
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... DRAWN TO SCALE) FILTER CAP) 7 ANALOG GND 47Ω A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE- BOARD GND LINES IS ALL THAT IS NECESSARY TO USE THE MC88921 IN A NORMAL DIGITAL ENVIRONMENT. 8 TBD TIMING SOLUTIONS BR1333 — REV 5 ...
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... X–TAL OSCILLATOR Figure 7. Typical MC88921/Pentium Microprocessor System Configuration TIMING SOLUTIONS BR1333 — REV 5 Pentium Microprocessor 66MHz 2X_Q PCLK SYNC Q1 Q2 33MHz Q3 9 MC88921 ASIC ASIC MEMORY MODULE MOTOROLA ...
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... AND -02 OBSOLETE, NEW STANDARD 751D-03. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 *MC88921/D* MC88921/D TIMING SOLUTIONS BR1333 — REV 5 ...