W986416DH-7 Winbond, W986416DH-7 Datasheet
W986416DH-7
Available stocks
Related parts for W986416DH-7
W986416DH-7 Summary of contents
Page 1
... Self Refresh Command ..................................................................................................................10 Power Down Mode..........................................................................................................................10 No Operation Command.................................................................................................................11 Deselect Command ........................................................................................................................11 Clock Suspend Mode......................................................................................................................11 8. TABLE OF OPERATING MODES .....................................................................................................12 Simplified State Diagram ................................................................................................................ CHARACTERISTICS ...................................................................................................................14 Absolute Maximum Rating..............................................................................................................14 10. RECOMMENDED DC OPERATING CONDITIONS ........................................................................ BANKS Publication Release Date: April 11, 2002 - 1 - W986416DH 16 BITS SDRAM Revision A4 ...
Page 2
... Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................42 Timing Chart of Burst Stop Cycle (Precharge Command)..............................................................43 CKE/DQM Input Timing (Write Cycle) ............................................................................................44 CKE/DQM Input Timing (Read Cycle) ............................................................................................45 Self Refresh/Power Down Mode Exit Timing..................................................................................46 16. PACKAGE DIMENSION ..................................................................................................................47 54L TSOP (II)-400 mil.....................................................................................................................47 17. VERSION HISTORY ........................................................................................................................ W986416DH ...
Page 3
... Sequential and Interleave burst Burst read, single write operation 3. AVAILABLE PART NUMBER PART NUMBER W986416DH-5 W986416DH-6 W986416DH-6I W986416DH-7 W986416DH-7L Byte data controlled by DQM Power-down Mode Auto-precharge and controlled precharge 4K refresh cycles/64 mS Interface: LVTTL Packaged in TSOP II 54-pin, 400 mil - 0.80 SPEED ( SELF REFRESH CURRENT (MAX ...
Page 4
... W986416DH DQ15 DQ14 DQ13 DQ12 48 DQ11 DQ10 ...
Page 5
... Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from V immunity. Separated ground from V immunity. No connection - 5 - W986416DH DESCRIPTION A11. Column address: A0 A7. CAS and WE define the In write ...
Page 6
... COLUMN DECODER CELL ARRAY BANK #0 SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN DECODER CELL ARRAY BANK #2 SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 256 * W986416DH COLUMN DECODER CELL ARRAY BANK #1 SENSE AMPLIFIER DQ0 DQ BUFFER DQ15 UDQM LDQM COLUMN DECODER CELL ARRAY ...
Page 7
... After power up, an initial pause of 200 S is required followed and WE at the positive edge of the clock. The address input data ). The maximum time that each bank can be held active is RRD - 7 - W986416DH CC delay. WE pin voltage RCD high write operation ( WE Publication Release Date: April 11, 2002 Revision A4 +0 ...
Page 8
... Latency in a burst read cycle, interrupted by Burst Stop Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored. The Mode Register sets type of burst (sequential or interleave) and and CAS high with - 8 - W986416DH CS and CAS while holding CS , CAS ...
Page 9
... (disturb addresses are A0, A1 and A2) No address carry from ACCESS ADDRESS W986416DH BUST LENGTH Publication Release Date: April 11, 2002 Revision A4 ...
Page 10
... When using the Auto-precharge Command, DAL RAS and WE are low and CS , RAS , CAS . The input buffers need (min (min.). CKS W986416DH and t are satisfied. This is RP CAS is high at the and CKE held low with the REF ...
Page 11
... The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited low with RAS , CAS , and is brought high, the RAS , CAS , and - 11 - W986416DH WE held high at the rising WE signals become don't Publication Release Date: April 11, 2002 Revision A4 ...
Page 12
... W986416DH RAS CAS ...
Page 13
... REF IDLE Power Down CKE Active ROW Power ACTIVE CKE Down Read WRITE READ Write READA WRITEA Precharge Precharge - 13 - W986416DH CBR Refresh Read CKE READ SUSPEND CKE CKE READA SUSPEND CKE Automatic sequence Manual input Publication Release Date: April 11, 2002 Revision A4 ...
Page 14
... RECOMMENDED DC OPERATING CONDITIONS ( for -5/-6/-7/-7L - for -6I PARAMETER Supply Voltage (Normal operation) Supply Voltage for W986416DH-7L During Self Refresh Mode Supply Voltage for I/O Buffer Input High Voltage Input Low Voltage Note: V (max +1.2V for pulse width < ...
Page 15
... CK I 185 CC4 (t = min 130 CC5 Standard(-5/-6/- CC6 Low Power(-6I/-7L CC6L SYMBOL W986416DH -6/-6I -7/-7L UNIT MAX. MAX 165 145 120 110 1 1 400 400 µA MIN. MAX. ...
Page 16
... T t 1.5 1 1.5 1 1.5 1.5 CKS CKH t 1.5 1.5 CMS CMH REF RSC - 16 - W986416DH -7/-7L UNIT NOTE MIN. MAX 100000 20 1 Cycle 1000 7 1000 5 0.5 10 1.5 1 1.5 1 1 ...
Page 17
... CLK measured from the negative edge to the positive edge referenced and V (simultaneously) while all input signals are held in the “NOP” state. The CLK CCQ 1.4V See diagram below 2.4V/0. 1.4V 1 ohms AC TEST LOAD and W986416DH CONDITIONS 50 ohms 30pF Publication Release Date: April 11, 2002 Revision A4 CK (min.). IH (max.). IL ...
Page 18
... Bust Stop Command to Last Valid Data Out Read with Auto-precharge Command to Active/Ref Command Write with Auto-precharge Command to Active/Ref Command Latency W986416DH 1 Cycle Cycle + nS ...
Page 19
... RAS CAS WE A0-A10 BS0 CKS CKH CKE t t CMS CMH t t CMS CMH t t CMS CMH t t CMS CMH CKH CKS t CKS - 19 - W986416DH CMH CMS t CKH Publication Release Date: April 11, 2002 Revision A4 ...
Page 20
... Timing Waveforms, continued Read Timing CLK CS RAS CAS WE A0-A10 BS0 Read Command Read CAS Latency Valid Data-Out - 20 - W986416DH Valid Data-Out Burst Length ...
Page 21
... Valid Data- Valid Data- Valid Data- Valid Data- W986416DH t t CMH CMS Valid Valid Data-in Data- Valid Data- Valid Valid Data-in Data-in ...
Page 22
... OH Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out Valid Valid Data-Out Data-Out - 22 - W986416DH OPEN Valid Data-Out OPEN Valid Data-Out ...
Page 23
... Reserved Reserved A0 A9 Single Write Mode A0 0 Burst read and Burst write Burst read and single write A0 Publication Release Date: April 11, 2002 - 23 - W986416DH next command Interleave Reserved A0 Revision A4 ...
Page 24
... RP t RAS t t RCD RCD RBb RAc CBx RBb RAc t AC bx1 aw0 aw1 aw2 aw3 bx0 t RRD Active Precharge Active Read Precharge - 24 - W986416DH RAS RAS t RCD RBd CAy RBd CBz t AC ...
Page 25
... RAS t RCD t RCD RAc CBx RAc aw0 aw1 aw2 aw3 bx0 bx1 t RRD AP* Active Read AP W986416DH RAS RAS t RCD RAe RBd CBz CAy RAe RBd ...
Page 26
... RP RAS t RCD RBb RBb CBy ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 t RRD Precharge Active Read - 26 - W986416DH RAS t RCD RAc RAc CAz t AC by4 by5 by6 by7 CZ0 Active Read Precharge ...
Page 27
... RAS RP t RCD RBb RBb CBy t CAC ax3 ax4 ax0 ax2 ax5 ax6 ax7 ax1 t RRD AP* Active Read * AP is the internal precharge start timing - 27 - W986416DH RAS t RCD RAc RAc CAz t CAC t CAC by0 by1 by4 by5 ...
Page 28
... RC t RAS t RCD RBb RBb CBy ax4 ax5 ax6 ax7 by0 by1 by2 t RRD Precharge Active Write - 28 - W986416DH RAS t RCD RAc RAc CAz by3 by4 by5 by6 by7 CZ0 CZ1 Active Write ...
Page 29
... RC t RAS t RCD RBb CBy RBb ax4 by2 ax5 ax6 ax7 by0 by1 t RRD AP* Active Write * AP is the internal precharge start timing - 29 - W986416DH RAS t RCD RAb CAz RAc by5 by3 by4 by6 by7 CZ0 Write ...
Page 30
... RAS t RCD CBx CAy CAm bx0 Ay0 Ay1 a2 bx1 Read Read Read * AP is the internal precharge start timing - 30 - W986416DH CBz am1 am2 bz0 bz1 bz2 bz3 Ay2 am0 Precharge Read AP* ...
Page 31
... MHz RAS CAy ax5 ax0 ax1 ax2 ax3 ax4 ay0 Write - 31 - W986416DH ay1 ay2 ay3 ay4 Precharge Publication Release Date: April 11, 2002 Revision A4 23 ...
Page 32
... Bank #2 Idle Bank #3 (CLK = 100 MHz RCD RAb RAb aw0 aw1 aw2 aw3 AP* Active * AP is the internal precharge start timing - 32 - W986416DH RAS CAx t AC bx1 bx2 bx3 bx0 Read AP* 23 ...
Page 33
... RCD RAb RAb CAx aw2 aw3 bx0 Active Write AP the internal precharge start timing - 33 - W986416DH RAS RP RAc RAc bx1 bx3 bx2 Active AP* Publication Release Date: April 11, 2002 Revision A4 ...
Page 34
... Operating Timing Example, continued Autorefresh Cycle CLK RAS CAS WE BS0,1 A10 A0-A9 DQM CKE DQ All Banks Auto Prechage Refresh (CLK = 100 MHz W986416DH Auto Refresh (Arbitrary Cycle) ...
Page 35
... A10 A0-A9 DQM t SB CKE t CKS DQ All Banks Self Refresh Precharge Entry (CLK = 100 MHz CKS Self Refresh Cycle - 35 - W986416DH CKS Operation Cycle Arbitrary Cycle Publication Release Date: April 11, 2002 Revision A4 23 ...
Page 36
... Bank #1 Bank #2 Idle Bank #3 (CLK = 100 MHz CBw CBx t AC av0 av1 av3 aw0 ax0 av2 Single Write - 36 - W986416DH CBz CBy t AC ay0 az1 az2 az3 az0 Read 23 ...
Page 37
... When CKE goes high, command input must be No operation at next CLK rising edge. (CLK = 100 MHz CAa t CKS ax0 ax1 ax2 ax3 Precharge Read - 37 - W986416DH RAa RAa CAx CKS NOPActive Precharge Standby Power Down mode ...
Page 38
... Act Act represents the Write with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command W986416DH Act Act AP Act ...
Page 39
... represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. the start of internal precgarging must be at least W986416DH Act Act AP Act t RP ...
Page 40
... Command DQM DQ (2) CAS Latency Command DQM Command DQM DQ Note: The Output data must be masked by DQM to avoid I/O conflict Read Write Read Write Read Write Read Write W986416DH ...
Page 41
... Command DQM Command Write DQM D0 DQ (2) CAS Latency = 3 Write ( a ) Command DQM DQ D0 Write ( b ) Command DQM Read Read Read Q0 Q1 Read W986416DH Publication Release Date: April 11, 2002 Revision A4 11 ...
Page 42
... Timing Chart of Burst Stop Cycle (Burst Stop Command (3) Read cycle ( a ) CAS latency =2 Read Command CAS latency = 3 Read Command DQ (2) Write cycle Write Command Note: BST BST BST BST represents the Burst stop command - 42 - W986416DH ...
Page 43
... DQM CAS latency = 3 Write Commad DQM D0 DQ Note: PRCG PRCG PRCG PRCG PRCG represents the Precharge command - 43 - W986416DH Publication Release Date: April 11, 2002 Revision A4 11 ...
Page 44
... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM DQM MASK ( DQM MASK CKE MASK ( CKE MASK ( W986416DH CKE MASK ...
Page 45
... External CLK Internal CKE DQM CLK cycle No. External CLK Internal CKE DQM W986416DH Open Open Open Publication Release Date: April 11, 2002 Revision A4 ...
Page 46
... Self Refresh mode NOP Command (min (min (min (min)+t (min NOP Command Input Buffer Enable (min (min (min)+t (min Command Input Buffer Enable Represents the No-Operation command Represents one command - 46 - W986416DH ...
Page 47
... MAX. MIN. NOM. 1.20 0.15 0.05 0.10 0.002 0.004 1.00 0.039 0.24 0.32 0.40 0.009 0.012 0.006 0.15 22.12 22.22 22.62 0.871 0.875 10.06 10.16 10.26 0.396 0.400 11.56 11.76 11.96 0.455 0.463 0.80 0.0315 0.40 0.50 0.60 0.016 0.020 0.80 0.032 0.10 0.71 0.028 - 47 - W986416DH MAX. 0.047 0.006 0.016 0.905 0.404 0.471 0.024 0.004 Publication Release Date: April 11, 2002 Revision A4 ...
Page 48
... TEL: 1-408-9436666 FAX: 1-408-5441798 Winbond Electronics Corporation Japan 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 - 48 - W986416DH DESCRIPTION capacitance value Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No ...