UPD6125A Renesas Electronics Corporation., UPD6125A Datasheet

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SINGLE CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION DESCRIPTION The PD6125A and 6126A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs, stereos, cassette decks, air conditioners, etc. These microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, ...

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ORDERING INFORMATION Part Number PD6125ACA-XXX PD6125AG-XXX PD6126AG-XXX Remark XXX indicates a ROM code suffix. PIN CONFIGURATION (Top View) PD6125A • S-IN S-OUT 6 REM ...

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BLOCK DIAGRAM ROM D.P. L ROM H D.P. PC(L) PC(H) TIMER TIMER (L) (H) 10 bit OSC MOD OSC-IN S-OUT REM OSC-OUT Note PD6125A: I/O -I PD6126A: I/O -I DIFFERENCES AMONG PRODUCTS Part ...

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PROGRAM COUNTER (PC) ……… 10 BITS The program counter (PC binary counter, which holds the address information for the program memory. Figure 1-1. Program Counter Organization Normally, the program counter contents ...

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PROGRAM MEMORY (ROM) ……… 1002 STEPS The program memory (ROM) is configured in 10 bits steps addressed by the program counter. Program and table data are stored in the program memory. Figure 3-1. Program Memory Map 000H ...

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DATA POINTER ( for the data memory can serve as the data pointer for the ROM specifies the low-order 8 bits in the ROM address. The high-order 2 ...

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SYSTEM CLOCK GENERATION CIRCUIT The system clock generation circuit consists of an oscillation circuit, which uses a ceramic resonator (400kHz to 500kHz). Figure 9-1. System Clock Generation Circuit OSC-IN OSC-OUT In the STOP mode (oscillation stop HALT instruction), the ...

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TIMER The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier ...

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PIN FUNCTIONS 11.1 K Pin (P ) I/O 0 This is the 8-bit I/O pin for key-scan output. When the control register (P be used as an 8-bit input pin. When the port is set for the input mode, ...

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I/O Pin ( Note ) are input/output pins for adding a key matrix. The LSB of control registers input and output modes. When in input mode, all pins are pulled ...

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K Pin ( This is the 4-bit pin for key input. All of these pins can be pulled down to the 11.6 K Pull-Down Resistor Organization I Pin K pull-down I resistor switch ...

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S-OUT Pin By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication is in progress. The S-OUT pin is a CMOS output pin. The S-OUT pin goes high on reset. ...

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PORT REGISTER ( I/ and the control register are handled as port registers. I/O I The table below shows the relations between the port registers and pins. Table 12-1. Relations between Port Registers and ...

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CONTROL REGISTER ( The control register contains of 10 bits. The controllable items are shown in Table 13-1. Table 13-1. Control Register (P1) Bit Name Test mode – 0 Set Be ...

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STANDBY FUNCTION (HALT INSTRUCTION) The PD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption, when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode). In the ...

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AC PIN (ALL CLEAR PIN) Internal part of the CPU including the program counter can be reset by setting the AC pin to the low level. Watchdog Timer Function A power-on reset function and a CR watchdog timer function, ...

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MASK OPTIONS (PLA DATA) The following items can be selected by mask option selection: • Provide/not provide K , I/O, S-IN pin pull-down resistor I • Carrier duty selection (1/2, 1/ • Hang-up detection specification Mask option ...

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Figure 16-1. Hang-up Detection K K output signal I/O0 K output signal I/O1 K output signal I/O2 K output signal I/O3 K output signal I/O4 K output signal I/O5 K output signal I/O6 K output signal I/O7 K input/output selection ...

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PROGRAM DEVELOPMENT TOOLS To develop programs for the PD6125A, 6126A, an assembler and an emulator for the PD612X series are available from I.C. Corp. For details, contact IC Corp. 18. ORDERING ROM CODE <1> To generate the data required ...

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INSTRUCTION SET Accumulator Manipulation Instructions R – ANL A, R D00 r ANL D10 0 ANL D30 0 ANL A, #data D31 A, R ORL E00 ...

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Branch Instructions R – JMP0 addr 411 Note JMP0 R – – addr 611 Note JC R – – r JNC addr 631 Note JNC R – – addr 711 Note JF R ...

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TYPICAL APPLICATION CIRCUIT EXAMPLE (1) PD6125A application circuit example SE303A-C SE307-C SE313 V DD SE1003-C (no carrier) 2SC2001, 3616 2SD1513, 1614 2SD1616 2.0 (with carrier 0.1 F Caution The ...

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PD6126A application circuit example SE303A-C 7 SE307-C SE313 V DD SE1003-C (no carrier) 2.0 8 2SC2001, 3616 9 2SD1513, 1614 2SD1616 (with carrier) 10 100 100 pF ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Supply voltage V Input voltage V Operating ambient temperature T Storage temperature T Caution If the rated value of even one of the above parameters is exceeded ...

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DC Characteristics (V = 3.0V 455kHz OSC Parameter Symbol Supply voltage V Current dissipation 1 I Current dissipation 2 I REM high level output current I OH1 REM low level output current I S-OUT high level ...

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CHARACTERISTICS CURVE (Target Value characteristic examples (REM ± 3 ° 4.0 DD 3.0 2.0 1.0 0 0.2 0.4 0.6 0.8 Low-level output voltage V OL ...

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characteristic examples ( ± 3 ° –4.0 –3.0 –2.0 –1.0 0 2.2 2.4 2.6 2.8 3.0 High-level output voltage V [V] OH PD6125A, ...

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PACKAGE DRAWINGS (1) PD6125A package drawings (1/2) 16-Pin Plastic SOP (300 mil) (units in mm) 24 PIN PLASTIC SHRINK DIP (300 mil NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) ...

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PIN PLASTIC SOP (300 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition PD6125A, 6126A detail ...

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PD6125A package drawings (2/2) 24-PIN SHRINK DIP FOR ES (REFERENCE) (Unit in mm) 30 fig. blank c PD6125A, 6126A ...

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CERAMIC MINI FLAT PACKAGE FOR ES (REFERENCE) (Unit in mm) PD6125A, 6126A 31 ...

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PD6126A package drawings (1/2) 20-Pin Plastic SOP (300 mil) (units in mm) 28 PIN PLASTIC SOP (375 mil NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true ...

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PD6126A package drawings (2/2) 28-PIN CERAMIC SOP FOR ES (REFERENCE) (Unit in mm) PD6125A, 6126A fig. blank f 33 ...

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RECOMMENDED SOLDERING CONDITIONS It is recommended that PD6125A and 6126A be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document Semiconductor Device Mounting Technology Manual (C10535E). For other soldering methods and conditions, ...

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APPENDIX PD612X SERIES PRODUCTS Part Number PD6124A Item ROM capacity 1002 10 bits (Mask ROM) RAM capacity 32 5 bits I/O pins 8 pins (K I/O0-7 S-IN pins Provided Current consumption STOP) (MAX.) OSC S-IN high ...

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PD6125A, 6126A ...

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PD6125A, 6126A 37 ...

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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...

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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...

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The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product ...