K4S281632D Samsung, K4S281632D Datasheet
K4S281632D
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K4S281632D Summary of contents
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... K4S281632D 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM * Samsung Electronics reserves the right to change products or specification without notice. LVTTL Rev. 0.1 Sept. 2001 CMOS SDRAM Rev. 0.1 Sept. 2001 ...
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... K4S281632D Revision History Revision 0.0 (Mar. 06, 2001) Revision 0.1 (Sep. 06, 2001) • Redefined IDD1 & IDD4 in DC Characteristics • Changed the Notes in Operating AC Parameter. < Before > 5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After > 5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. ...
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... CKE * Samsung Electronics reserves the right to change products or specification without notice. GENERAL DESCRIPTION The K4S281632D is 134,217,728 bits synchronous high data rate Dynamic RAM organized 2,097,152 words by 16 bits, fabricated with SAMSUNG s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle ...
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... K4S281632D PIN CONFIGURATION (Top view) PIN FUNCTION DESCRIPTION Pin Name CLK System clock CS Chip select CKE Clock enable Address Bank select address 0 1 RAS Row address strobe CAS Column address strobe WE Write enable L(U)DQM Data input/output mask DQ ~ Data input/output ...
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... (min) = -2.0V AC. The undershoot voltage duration Any input DDQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. The VDD condition of K4S281632D-60 is 3.135V~3.6V. CAPACITANCE (V = 3.3V Pin Clock RAS, CAS, WE, CS, CKE, DQM Address ...
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... Operating current I CC4 (Burst mode) Refresh current I CC5 Self refresh current I CC6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S281632D-TC** 4. K4S281632D-TL** 5. Unless otherwise noted, input swing IeveI is CMOS Test Condition Burst length = (min CKE ...
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... Output timing measurement reference level Output load condition Output 870 (Fig output load circuit Notes : 1. The DC/AC Test Output Load of K4S281632D-60/55 is 30pF. 2. The VDD condition of K4S281632D-60/55 is 3.135V~3.6V. OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay ...
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... K4S281632D AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter Symbol CAS latency=3 CLK cycle time CAS latency=2 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=3 Output data hold time CAS latency=2 CLK high pulse width CLK low pulse width Input setup time ...
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... K4S281632D IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197.0 1.8 -67.3 -226.2 1.65 -73.0 -248.0 1.5 -77.9 -269.7 1.4 -80.8 -284.3 1.0 -88.6 -344.5 0.0 -93.0 -502.4 I Characteristics (Pull-down) OL 100MHz 100MHz Voltage 133MHz 133MHz Min Max (V) I (mA) I (mA) 0.0 0.0 0.0 0.4 27.5 70.2 0.65 41.8 107.5 0.85 51.6 133.8 1.0 58.0 151.2 1.4 70.7 187.7 1.5 72.9 194.4 1.65 75.4 202.5 1.8 77.0 208.6 1 ...
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... K4S281632D V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) DD 0.0 0.0 0.2 0.0 0.4 0.0 0.6 0.0 0.7 0.0 0.8 0.0 0.9 0.0 1.0 0.23 1.2 1.34 1.4 3.02 1.6 5.06 1.8 7.35 2.0 9.83 2.2 12.48 2.4 15.30 2.6 18.31 V Clamp @ CLK, CKE, CS, DQM & (V) I (mA) SS -2.6 -57.23 -2.4 -45.77 -2.2 -38.26 -2.0 -31.22 -1.8 -24.58 -1.6 -18.37 -1.4 -12.56 -1.2 -7.57 -1.0 -3.37 -0.9 -1.75 -0.8 -0.58 -0.7 -0.05 -0.6 0.0 -0.4 0.0 -0.2 0.0 0.0 0.0 Minimum V clamp current DD (Referenced Voltage I (mA) Minimum V clamp current -10 -20 -30 -40 -50 -60 Voltage I (mA) Rev. 0.1 Sept. 2001 ...
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... K4S281632D SIMPLIFIED TRUTH TABLE Command Register Mode register set Auto refresh Entry Refresh Self fefresh Bank active & row addr. Read & Auto precharge disable column address Auto precharge enable Write & Auto precharge disable column address Auto precharge enable Burst stop ...