S5L9274X01-E0R0 Samsung, S5L9274X01-E0R0 Datasheet

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S5L9274X01-E0R0

Manufacturer Part Number
S5L9274X01-E0R0
Description
Manufacturer
Samsung
Datasheet
DECODER FOR CD-MP3/CD-ROM
INTRODUCTION
of decoding compressed elementary bit stream as specified in ISO/IEC
standard. As a decoder for the DISC-MAN, it can provide you more small and
cheaper solution for MP3 player application.
S5L9274 is low voltage IC that can read MP3 and CD-ROM format discs and
can be applied to various products.
FEATURES
ORDERING INFORMATION
S5L9274 is a single chip ISO/IEC 11172-3 Layer III audio decoder, capable
Single-chip ISO/IEC 11172-3 Layer III Audio Decoder
Support All MPEG Bit Rates including free format
Support 32/44.1/48 kHz Sampling Frequency for MPEG Bit Stream
Support Single Channel, Dual Channel, Stereo and Joint Stereo
Any Combination of Intensity Stereo & MS Stereo is supported
Serial Host Interface
Simple Software for Micom
Support Off-chip DAC interface
Anti Shock Memory Controller
Power Save Mode : POWER-DOWN, SLEEP (when paused)
Use of Standard Crystal 16.9344MHz
16.9344MHz Clock Output Port
Soft Mute Function
CDFS(CD-ROM File System) Decoding
Low Power Dissipation : 171mW @3.0 volts
S5L9274X01-E0R0
Device
64-LQFP-1010
Package
Supply Voltage
2.8V
3.3V
64-LQFP-1010
Operating Temperature
-20 C
+75 C
S5L9274
1

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S5L9274X01-E0R0 Summary of contents

Page 1

... Anti Shock Memory Controller Power Save Mode : POWER-DOWN, SLEEP (when paused) Use of Standard Crystal 16.9344MHz 16.9344MHz Clock Output Port Soft Mute Function CDFS(CD-ROM File System) Decoding Low Power Dissipation : 171mW @3.0 volts ORDERING INFORMATION Device S5L9274X01-E0R0 Package Supply Voltage 64-LQFP-1010 2.8V S5L9274 64-LQFP-1010 Operating Temperature 3.3V ...

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S5L9274 FUNCTIONAL BLOCK DIAGRAM CD-MP3 Decoder Chip cdrUnit (CD-ROM Decoder) ckgUnit DRAM Bandwidth Estimated - 1.9M words/sec 2 Register Set IB OB read write read Channel Channel Channel memUnit (Memory Management Unit) DRAM Controller bits DRAM Figure1. ...

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DECODER FOR CD-MP3/CD-ROM APPLICATION DIAGRAM Test Pin Connection 40pF 2 16.9344MHz 3 40pF 820pF 10 940pF GND SCAN_EN 41 TEST2 42 TEST1 43 TEST0 GND XI XO XOUT CLK FILTER0 FILTER1 PLL_BYPASS S5L9274 3 ...

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S5L9274 PIN CONFIGURATION 1 VDD XOUT 4 CLK 5 RESETB 6 PLL0 VDDA 7 PLL0 VSSA 8 PLL0 VBBA 9 FILTER_0 10 PLL1 VDDA 11 PLL1 VSSA 12 PLL1 VBBA 13 FILTER_1 14 PLL_BYPASS 15 VSS ...

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DECODER FOR CD-MP3/CD-ROM PIN DESCRIPTION Pin No Symbol 1 VDD XOUT 5 CLK 6 RESETB 7 PLL0 VDDA 8 PLL0 VSSA 9 PLL0 VBBA 10 FILTER_0 11 PLL1 VDDA 12 PLL1 VSSA 13 PLL1 VBBA ...

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S5L9274 PIN DESCRIPTION (Continued) Pin No Symbol 33 VDD 34 MCU_CLK 35 MDAT 36 MCK 37 MLAT 38 MDOUT 39 MINT 40 SCAN_EN 41 TEST2 42 TEST1 43 TEST0 44 DDAT0 45 DDAT1 46 WEB 47 RASB 48 VSS 49 ...

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DECODER FOR CD-MP3/CD-ROM ABSOLUTE MAXIMUM RATINGS Parameter power supply voltage Input supply voltage Operating temperature Storage temperature ELECTRICAL CHARACTERISTICS Pin Number Pin 10, Pin11 Pin2, Pin3 Pin4,Pin19,Pin34,Pin38,Pin39,Pin28,Pin29 Pin18,Pin5 Pin20,Pin21,Pin22,Pin23 Pin6,Pin15,Pin40,Pin41,Pin42,Pin43 Pin35,Pin36,Pin37 Pin44,Pin45,Pin50,Pin51 Pin24,Pin25,Pin26,Pin27,Pin46,Pin47,Pin52,Pin53,Pin 54,Pin55,Pin56,Pin57,Pin58,Pin59,Pin60,Pin61,Pin62, Pin63 Symbol VDD VI 3.3V I/O ...

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S5L9274 V = 3.3 0.3V case of normal IO) DD Symbol Parameter V High level input voltage IH (LVCMOS interface) V Low level input voltage IL (LVCMOS interface) VT Switching threshold VT+ ...

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DECODER FOR CD-MP3/CD-ROM V = 3.3 0.3V, VEXT = 5+ 0.25V case of 5V-tolerant IO) DD Symbol Parameter Note1 V High level input voltage IH (LVCMOS interface) Note1 V Low level input ...

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S5L9274 OPERATION DESCRIPTION IO TIMING SPECIFICATION MCU Interface MCK MLT MDAT C1 C2 MCK MLT MDAT MDOUT C1 C2 MCK MLT MDAT Memory read command (8'h50) MDOUT Description for the memory ...

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DECODER FOR CD-MP3/CD-ROM POWER MANAGEMENT Power Save Modes Down : Master Clock Disabled. Whole chip is in reset state and clocking is disabled. (Host Interface ?, Clocks for CD-DSP chip ?) Mode : All units suspended except hifUnit and DRAM ...

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S5L9274 HOST MCU CONTROL SPACE Registers to control CD-ROM sector decoding // Read only registers (8'h20 H_MIN_R 8'h24 "minute" in the header of the sector being currently decoded. H_SEC_R 8'h25 "second" in the header of the sector being currently decoded. ...

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DECODER FOR CD-MP3/CD-ROM bit5 bit4 bit3 bit2 bit1 bit0 H_HEAD_W 8'hB2 bit7 bit6 bit5 bit4 bit3:0 H_OPSR_W 8'hB3 H_START_M 8'hB4 H_START_S 8'hB5 H_START_F 8'hB6 H_ECC_EN 8'hB7 bit7:1 bit0 default value : 0x00 BCKs. Data valid for the ...

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S5L9274 Registers to communicate with embedded DSP core // Read only registers (8'h00 H_OUT1_LOW 8'h01 H_OUT1_HIGH 8'h02 H_OUT2_LOW 8'h03 H_OUT2_HIGH 8'h04 H_OUT_XTRA 8'h05 H_EMPH 8'h06 // Write only registers (8'h80 H_SSPINT 8'h80 H_IN_LOW 8'h81 H_IN_HIGH 8'h82 H_IN_XTRA 8'h83 Registers for ...

Page 15

DECODER FOR CD-MP3/CD-ROM // Write only registers (8'h90 H_CD_START_H 8'h90 H_CD_START_L 8'h91 H_CD_END_H 8'h92 H_CD_END_L 8'h93 H_IB_START_H 8'h94 H_IB_START_M 8'h95 H_IB_START_L 8'h96 H_IB_END_H 8'h97 H_IB_END_M 8'h98 H_IB_END_L 8'h99 H_OBL_START_H 8'h9a H_OBL_START_M 8'h9b H_OBL_START_L 8'h9c H_OBL_END_H 8'h9d H_OBL_END_M 8'h9e H_OBL_END_L 8'h9f ...

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S5L9274 Registers to control DAC interface // Read only registers (8'h30 // Write only register (8`hB0) H_DAC_TYPE 8'hB0 // Write only registers (8'hC0 H_DACIF_nOE 8'hC0 Registers for configuration of clock // Read only registers (8'h40 // Write only registers (8'hD0 ...

Page 17

DECODER FOR CD-MP3/CD-ROM SETTING SYSTEM CLOCK FREQUENCY NOTE : ACLK : audio clock of BI9274X internal. CLK : system clock of BI9274X internal. MODE 1 - Dual PLL Mode A ( H_CKG_CMD0[2: PLL_BYPASS = LOW) ...

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S5L9274 MODE 3 - Single PLL Mode ( H_CKG_CMD0[2: PLL_BYPASS = LOW) H_PLL0_P0 H_PLL0_M0 H_PLL0_S0 Host Control H_PLL0_P1 H_PLL0_M1 H_PLL0_S1 H_CKG_DIV_XY H_CKG_CMD0 CLK (I) PIN SETTING ACLK_EXT ( MODE 4 - PLL BYPASS ...

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DECODER FOR CD-MP3/CD-ROM MICOM PROGRAMMING GUIDELINE Transferring Input Bitstream to S5L9274 Micom is allowed to initiate the transfer when the Input Buffer is in LOW state which is by the "Input Buffer State" Interrupt (See section skip function) from CD-MP3 ...

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S5L9274 Burst Transfer without the number of sectors being transferred. Verify the Input Buffer is in LOW state. The register H_IB_STATE tells Input Buffer (Empty, Low, or High). When there is any change in the H_IB_STATE, "Input Buffer " Interrupt ...

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DECODER FOR CD-MP3/CD-ROM CDFS Table Read BI9274X decodes File Allocation Table of CD-ROM and stores it to DRAM. Micom can DRAM to read the CDFS Table using register read protocol. (See Section MCU interface.) Setting DRAM Refresh Rate Micom can ...

Page 22

S5L9274 REGISTER H_CD_START H_CD_END H_IB_START H_IB_END H_OBL_START H_OBL_END H_OBR_START H_OBR_END A storage for CDFS Table which is decoded by S5L9274 is needed for Micom to access. CDFS Table also stored in OBR(Output Buffer Right Channel) and OBL(Output Buffer Channel). S5L9274 ...

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DECODER FOR CD-MP3/CD-ROM Data Structure of CDFS Table in DRAM Structure of CDFS Table divided into four areas : The Introduction Table Area, Table Area, File Table Area and Identifier Table Area. According to Figure , is a typical configuration ...

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S5L9274 Directory Table Directory Table follows the Introduction Table and comprises of consecutive directory records. There are as many directory records as the total number of directories in a table. Each directory record consists of 6 words as following. Address ...

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DECODER FOR CD-MP3/CD-ROM File Table File Table follows the Directory Table and comprises of consecutive file records. In the table, there are as many file records as the total number of MP3 file. Each file record of 6 words as ...

Page 26

... Can select one of the four preset refresh interval value 8d'19 * 8d'40 * 8d'0 * don't care * don't care * don't care * don't care * 8d'0 (8'hB0) *8'h91 for DAC in 9288 * 8'h72 // for SAMSUNG CD-DSP chip * 8'h18 // for MODE1 FORM1 * 8'bxxxxxxx1 // Enable ecc * 8'b0xxxxxxx * 8'b0xxxxxxx (8'hA6) * 8'bxxxxxx00 DECODER FOR CD-MP3/CD-ROM ...

Page 27

DECODER FOR CD-MP3/CD-ROM CDFS Decode Process Programming 1. Boot Process 2. Set Memory Map Address for File Table (Use default memory map for Input Buffer, and set map for output buffers as following :) H_OBL_START_L (8'h9C) H_OBL_START_M (8'h9B) H_OBL_START_H (8'h9A) ...

Page 28

S5L9274 H_OUT1_LOW (8'h01) H_OUT1_HIGH (8'h02) H_OUT2_LOW (8'h03 and F read are all AAh or BBh, it indicates CDFS decoding has been completed. If they are all AAh it indicates that this CD is not in a juliet ...

Page 29

DECODER FOR CD-MP3/CD-ROM TAG DECODE PROCESS ID3 TAG Version 1.xx 1. Boot Process 2. Remap : Configure Memory Map 3. Transfer the last sector of an MP3 file to S5L9274. 4. Write a sector size to registers IN1. 5. Issue ...

Page 30

S5L9274 4. Send Command DECODE_MP3. H_SSPINT (8'h80 ) 5. Micom reads CDFS Table and select a music to be play. 6. Micom set Total_Sector_Number as follows. Total_Sector_Number ia a value with 20bit range. H_IN_XTRA (8'h83) H_IN_HIGH (8'h82) H_IN_LOW (8'h81) 7. ...

Page 31

DECODER FOR CD-MP3/CD-ROM Skip Function 1. Micom controls servo system to stop feeding CD data to S5L9274. 2. Micom send a command "Pause". (This is for the purpose of audio fade-out.) H_SSPINT (8'h80) 3. Follow the sequence from step2 (Remap) ...

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S5L9274 Get Decoding Time for Display wait interrupt continuously during decoding process for time display. H_INT_READ (8'h51) S5L9274 send this interrupt about twice or three times per second. The exact period is determined by sampling frequency. but Micom doesn't need ...

Page 33

DECODER FOR CD-MP3/CD-ROM Interrupt handling There is one signal line for interrupt from BI9274X to Micom (MINT). When Micom is by BI9274X, it should read the interrupt source register in CD-MP3 (H_INT_READ 8'h51) which indicates the interrupt type to idendify ...

Page 34

S5L9274 Command Set Description Micom can send a command to S5L9274 by writing a command ID to H_SSPINT register. _SSPINT (8'h80 Host Command ID Command IDs --------------------------- 0x01 : DECODE_TAG 0x02 : DECODE_CDFS ...

Page 35

DECODER FOR CD-MP3/CD-ROM DRAM Interface 4Mbit( bit) DRAM 3.3V, 70ns, 1K refresh KM44V1000D (FP) KM44V1004D (EDO) S5L9274 DA0 - 9 DDAT0 - 3 RASB CASB OEB WEB Figure 3. Interface with 1Mx4bit DRAM 16Mbit( bit) DRAM ...

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S5L9274 S5L9274 DA0 - 9 DDAT0 - 3 S5L9274 DA0 - 9 DDAT0 - 3 36 16Mbit( bit) DRAM 3.3V, 70ns, 2K refresh KM48V2100C (FP) KM48V2104C (EDO) GND A10 DQ0 - 3 RASB RAS CASB ...

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