UPD70741GC-25-8EU Renesas Electronics Corporation., UPD70741GC-25-8EU Datasheet
UPD70741GC-25-8EU
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UPD70741GC-25-8EU Summary of contents
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The PD70741 (V821 32/16-bit RISC microprocessor that uses, as its processor core, the high- performance 32-bit microprocessor PD70732 (V810 peripheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serial interface, and interrupt controller. The ...
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ORDERING INFORMATION Part number PD70741GC-25-8EU 100-pin plastic LQFP (fine pitch) (14 PIN CONFIGURATION (TOP VIEW) 100-pin plastic LQFP (fine pitch) (14 PD70741GC-25-8EU RAS 77 UMWR 78 LMWR/WE 79 MRD 80 READY 81 CS0/REFRQ 82 CS1 83 CS2 ...
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PIN NAMES A0-A23 : Address Bus BLOCK : Bus Lock CLKOUT : System Clock Out CS0-CS3 : Chip Select D0-D15 : Data Bus DACK0, DACK1 : DMA Acknowledge DREQ0, DREQ1 : DMA Request HLDAK : Hold Acknowledge HLDRQ : Hold ...
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INTERNAL BLOCK DIAGRAM CLKOUT RESET WDTOUT WDT HLDAK BAU HLDRQ DREQ0, DREQ1 DACK0, DACK1 DMAC V821 RPU 4 CPU ICU (V810) UART CSI PORT DRAMC ROMC WCU/CS BIU PD70741 TO00,TO01 TCLR INTP00-INTP03, INTP10-INTP13 TXD ...
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PIN FUNCTIONS ........................................................................................................................ 1.1 Port Pins ......................................................................................................................................... 1.2 Non-Port Pins ................................................................................................................................. 1.3 Pin I/O Circuits and Processing of Unused Pins ...................................................................... 2. INTERNAL UNITS ...................................................................................................................... 2.1 Bus Interface Unit (BIU) ................................................................................................................ 2.2 Wait Control Unit (WCU) ............................................................................................................... 2.3 DRAM ...
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MEMORY ACCESS CONTROL FUNCTIONS .......................................................................... 6.1 DRAM Controller (DRAMC) ........................................................................................................... 6.1.1 Features .......................................................................................................................... 6.1.2 Address multiplexing function .................................................................................... 6.1.3 Refresh function ............................................................................................................ 6.1.4 Self-refresh function ...................................................................................................... 6.2 ROM Controller (ROMC) ................................................................................................................ 6.2.1 on-page/off-page decision ............................................................................................ 7. DMA FUNCTIONS (DMA ...
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ELECTRICAL SPECIFICATIONS .............................................................................................. 17. PACKAGE DRAWINGS ............................................................................................................. 107 18. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 108 PD70741 62 7 ...
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PIN FUNCTIONS 1.1 Port Pins Pin name Input/output P00 Input/output Port 0 P01 10-bit input/output port P02 Can be set for input/output bit. P03 P04 P05 P06 P07 P08 P09 Remark After a reset is released, each port pin ...
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Pin name Input/output CLKOUT Output System clock output CS0 Tristate output Chip select signal CS1 CS2 CS3 INTP00 Input Interrupt request input INTP01 INTP02 INTP03 INTP10 INTP11 INTP12 INTP13 NMI Input Nonmaskable interrupt request input REFRQ Tristate output Refresh request ...
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Pin I/O Circuits and Processing of Unused Pins Table 1-1 shows the I/O circuit type of each pin and the processing for unused pins. Figure 1-1 shows the I/O circuit of each type. Table 1-1. I/O Circuits Type of ...
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Type P-ch IN N-ch Type 2 IN Schmitt trigger input with hysteresis characteristics Type Data P-ch Output N-ch disable Push-pull output which can output high impedance (Both the positive and negative channels are off.) ...
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INTERNAL UNITS 2.1 Bus Interface Unit (BIU) Controls the pins of the address bus, data bus, and control bus. A bus cycle activated by the CPU or DMAC is controlled via the WCU, DRAMC, and ROMC. 2.2 Wait Control ...
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Watchdog Timer (WDT) This block incorporates an 8-bit watchdog timer to detect a program hanging up or system errors. If the watchdog timer overflows, the WDTOUT pin becomes active. 2.10 Clock Generator (CG) Supplies clock pulses at a frequency ...
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CPU FUNCTIONS The CPU has functions equivalent to those of the V810 microprocessor, designed for built-in control. It offers bit string instructions, floating-point instructions, and quick real-time response. 3.1 Features The features of the CPU are: • High-performance 32-bit ...
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Memory map Figure 3-1 shows the memory map of the V821. The internal 4-Gbyte memory space is divided into blocks of 1G byte each. Each block has a linear address space of 16M bytes. (The lower 24 bits of ...
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I/O map Figure 3-2 shows the I/O map of the V821. The internal 4-Gbyte memory space is divided into blocks of 1G byte each. Each block has a linear address space of 16M bytes. (The lower 24 bits of ...
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CPU Register Set The registers of the V821 belong to one of two sets, the general-purpose program register set and the dedicated system register set. All registers are 32 bits in wide. Program register set 31 r0 Zero Register ...
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Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers The V821 has 32 general-purpose registers, r0-r31. These registers can be used for data or address variables. Registers r0 and r26-r30 are ...
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System register set System registers are used to control the state of the CPU and store interrupt information. Table 3-2. System Register Numbers No. Register name 0 EIPC Registers for saving the current status upon the occurrence of an ...
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Built-in Peripheral I/O Registers The built-in peripheral I/O registers are allocated to the 256-byte area between C0000000H and C00000FFH in the 1-Gbyte space between C0000000H and FFFFFFFFH. Starting from address C0000100H, 256-byte images are created every 256 bytes. The ...
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Table 3-3. Built-in Peripheral I/O Registers (1/2) Address Function register name C0000010 Port mode control register 0 C0000012 Port mode register 0 C0000014 Port register 0 C0000020 Bus cycle type control register C0000022 Programmable wait control register 0 C0000024 Programmable ...
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Table 3-3. Built-in Peripheral I/O Registers (2/2) Address Function register name C0000084 Reception buffer C0000086 Reception buffer L C0000088 Transmission shift register C000008A Transmission shift register L C0000090 Synchronous serial interface mode register C0000092 Serial I/O shift register C00000A0 Baud ...
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Data Types 3.5.1 Data types The data types supported by the V821 are as follows: • Integer (8, 16, 32 bits) • Unsigned integer (8, 16, 32 bits) • Bit string • Single-precision floating-point data (32 bits) (1) Data ...
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Integer In the V821, all integers are expressed in the two’s-complement binary notation, and are composed of either 8 bits, 16 bits bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered ...
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First-word address (0s in bits 1 and 0) In-word bit offset (0 to 31) Bit length ( (5) Single-precision floating-point data This data type is 32 bits long and its ...
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Cache Figure 3-3 shows the instruction cache configuration provided to the V821. 31 Memory address Tag memory (ICHT27 to ICHT0 Entry 0 TAG31 to TAG10 Entry 1 128 entries Entry 127 Valid bits (1 bit for ...
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INTERRUPT/EXCEPTION HANDLING FUNCTIONS The V821 features an interrupt controller (ICU) that is dedicated to interrupt handling. The V821 thus supports a powerful interrupt handling function capable of handling interrupt requests issued sources. As referred to ...
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Type Category Group Priority in group Reset Interrupt - - RESET Non- Interrupt - - NMI maskable Software Exception - - TRAP1nH exception - - TRAP0nH Exception Exception - - DP-EX trap - - AD- I-OPC - - ...
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Type Category Group Priority in group Maskable Interrupt GR3 3 RESERVED 2 INTOV0 1 INTSER 0 INTP13 GR2 3 INTSR 2 INTST 1 INTCSI 0 INTP12 GR1 3 INTDMA 2 INTP00/ INTCC00 1 INTP01/ INTCC01 0 INTP11 GR0 3 INTCM1 ...
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WAIT CONTROL FUNCTIONS The wait control unit (WCU) manages the four blocks corresponding to the four chip select signals, generates the chip select signals, performs wait control, and selects the bus cycle types. 5.1 Features • Able to control ...
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Table 5-1. Bus Cycles during Which the Wait Function Is Effective Bus cycle SRAM (ROM) cycle (Blocks 0-3) DRAM cycle (Block 0) off-page on-page Page-ROM cycle (Block 3) off-page on-page External I/O cycle (Blocks 0-2) Internal I/O cycle (Block 3) ...
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MEMORY ACCESS CONTROL FUNCTIONS 6.1 DRAM Controller (DRAMC) The DRAM controller (DRAMC) generates the REFRQ, RAS, LCAS, and UCAS signals, and controls access to DRAM. Access to DRAM is achieved by multiplexing the DRAM row and column addresses and ...
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Table 6-1. Examples of DRAM and Address Multiplexing Width DRAM capacity (in bits) and configuration Address multiplexing width 256 K 8 bits bits - - 10 bits - - 11 bits - 6.1.3 Refresh function DRAMC ...
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Figure 6-2. on-page/off-page Decision When ROM Having a Page Access Function Is Connected (1) For 16-Mbit ROM (1-Mbit 16) Internal mrq a31 a30 address latch (Same address block) Setting of the Memory access PRC register Comparison Compa- rison V821 output ...
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DMA FUNCTIONS (DMA CONTROLLER) The V821 includes a DMA (Direct Memory Access) controller that executes and controls DMA transfer. The DMAC (DMA controller) transfers data between memory and I/O, or within memory, based on DMA requests issued by the ...
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Figure 7-1. Block Diagram of DMAC I/O ROM RAM I/O I/O 36 Bus interface Address control DMA source section address registers Data control section DMA destination address registers Count control section DMA byte count registers Channel control section DMA channel ...
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SERIAL INTERFACE FUNCTION 8.1 Features The V821 provides two transmission and reception channels as part of its serial interface function. The two interface modes listed below are supported, one channel being provided for each mode. The two modes operate ...
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Figure 8-1. Block Diagram of Asynchronous Serial Interface 16/8 Reception buffer Reception RXD shift register TXD Reception control parity check Internal bus RXB 16/8 8 RXE PS EBS CL RXBL ASIS TXS Transmission PE FE OVESOT shift ...
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Synchronous Serial Interface (CSI) 8.3.1 Features High-speed transfer 6.25 Mbps maximum (when /2 is used with Half-duplex communication Character length: 8 bits Switchable between the MSB and LSB to lead data transfer Allows selection between external serial clock input ...
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Baud Rate Generator (BRG) 8.4.1 Configuration and function With the serial interface, a serial clock chosen from the baud rate generator output and clocks generated using the system clock ( ) can be used as a baud rate. A ...
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TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) The real-time pulse unit (RPU) measures pulse intervals and frequencies, and outputs programmable pulses capable of 16-bit measurement. It can also generate various types of pulses, such as interval pulse and one-shot ...
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Figure 9-2. Timer 1 (16-Bit Interval Timer Note m/16 /4 m/32 /8 Note Internal count clock Remark : System clock 42 TM1 (16 bits) Clear and start INTCM1 CM1 PD70741 ...
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WATCHDOG TIMER FUNCTIONS The watchdog timer is intended to prevent program crash and deadlock. 10.1 Features • The following three different time-out time values can be specified: 10.5 ms, 41.9 ms, and 167.8 ms (when system clock = 25 ...
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Watchdog timer One of the watchdog timer functions is to secure the oscillation settling time of the system clock. When the system is reset or placed in STOP mode, the timer is cleared to 00H. The watchdog timer behaves ...
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PORT FUNCTIONS The V821 pins are dual-function pins that can function as both port and control pins. See Chapter 1 for details of each pin. 11.1 Features • 10 input/output ports (P00 to P09) Write Latch Figure 11-1. Configuration ...
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CLOCK GENERATION FUNCTIONS The clock generator generates and controls the internal clock pulse ( ) for the CPU and other built-in hardware units. 12.1 Features Frequency multiplication (5 times) using a PLL (phase locked loop) synthesizer Clock sources • ...
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STANDBY FUNCTIONS The V821 supports three standby modes to suppress power dissipation. In these standby modes, the operation of the clock is controlled. The HALT instruction is used to select a standby mode. Mode switching is controlled using the ...
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Table 13-1. Clock Generator Operation under Standby Control Clock source Standby mode PLL mode Resonator- Ordinary based HALT oscillation IDLE STOP External clock Ordinary HALT IDLE STOP Direct mode Ordinary HALT IDLE STOP Remark o : Operating : Stopped Table ...
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RESET FUNCTIONS Inputting a low level to the RESET pin triggers a system reset, thus initializing the on-chip hardware. When the RESET pin is driven from a low level to a high, the CPU starts program execution. The registers ...
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INSTRUCTION SET 15.1 Instruction Format The V821 instructions are formatted in either 16 bits or 32 bits. Examples of the 16-bit format instruction are binomial operation, control, and conditional branch; those for the 32-bit format are load/store, I/O manipulate, ...
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Intermediate jump instruction format (Format IV) This format consists of one 6-bit field to hold an operation code and one 26-bit field to hold a displacement (with its LSB masked to 0). 32-bit instructions use this format ...
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Instruction Mnemonic (In Alphabetical Order) The list of mnemonics is shown below. This section lists the instructions incorporated in the V821 along with their operations. The instructions are listed in the instruction mnemonic’s alphabetical order to allow users to ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (1/9) Instruction Operand (s) Format mnemonic ADD reg1, reg2 ADD imm5, reg2 II ADDF.S reg1, reg2 VII ADDI imm16, reg1, reg2 V AND reg1, reg2 I ANDBSU - II ANDI imm16, reg1, reg2 ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (2/9) Instruction Operand (s) Format mnemonic BH disp9 BL disp9 BLE disp9 BLT disp9 BN disp9 BNC disp9 BNE disp9 BNH disp9 BNL disp9 BNV disp9 BNZ disp9 BP disp9 BR disp9 BV ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (3/9) Instruction Operand (s) Format mnemonic CVT.SW reg1, reg2 VII CVT.WS reg1, reg2 VII DIV reg1, reg2 DIVF.S reg1, reg2 VII DIVU reg1, reg2 HALT - II IN.B disp16 [reg1], reg2 VI IN.H ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (4/9) Instruction Operand (s) Format mnemonic IN.W disp16 [reg1], reg2 JAL disp26 JMP [reg1] JR disp26 LD.B disp16 [reg1], reg2 LD.H disp16 [reg1], reg2 LD.W disp16 [reg1], reg2 ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (5/9) Instruction Operand (s) Format mnemonic LDSR reg2, regID II MOV reg1, reg2 I MOV imm5, reg2 II MOVBSU - II MOVEA imm16, reg1, reg2 V MOVHI imm16, reg1, reg2 V MUL reg1, ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (6/9) Instruction Operand (s) Format mnemonic NOTBSU - OR reg1, reg2 ORBSU - ORI imm16, reg1, reg2 ORNBSU - OUT.B reg2, disp16 [reg1] OUT.H reg2, disp16 [reg1] OUT.W reg2, disp16 [reg1 ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (7/9) Instruction Operand (s) Format mnemonic RETI - II SAR reg1, reg2 SAR imm5, reg2 II SCH0BSU - II SCH0BSD - II SCH1BSU - II SCH1BSD - II SETF imm5, reg2 II SHL ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (8/9) Instruction Operand (s) Format mnemonic SHL imm5, reg2 SHR reg1, reg2 SHR imm5, reg2 ST.B reg2, disp16 [reg1] ST.H reg2, disp16 [reg1] ST.W reg2, disp16 [reg1] STSR regID, reg2 SUB reg1, reg2 ...
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Table 15-1. Instruction Mnemonics (In Alphabetical Order) (9/9) Instruction Operand (s) Format mnemonic SUBF.S reg1, reg2 VII TRAP vector II TRNC.SW reg1, reg2 VII XOR reg1, reg2 I XORBSU - II XORI imm16, reg1, reg2 V XORNBSU - II CY ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T Parameter Symbol Supply voltage V DD Input voltage V I Clock input voltage V K Output voltage V O Operating ambient temperature T A Storage temperature T stg Cautions 1. Do not connect ...
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CAPACITANCE ( +5 Parameter Symbol Input capacitance C I Input/output capacitance Conditions MIN MHz PD70741 MAX. Unit ...
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AC CHARACTERISTICS (T = - Test Input Waveform (Other than RESET, NMI, and INTPn) Parameter Input rise time Input fall time Test Input Waveform (RESET, NMI, and INTPn) Parameter ...
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RECOMMENDED OSCILLATION CIRCUIT (a) Connecting a ceramic resonator (Murata Mfg. Co., Ltd -20 to +80 C, TDK Corp Cautions 1. The oscillation circuit should be placed as close to the X1 and X2 pins as possible. ...
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External clock input Open High-speed CMOS inverter External clock PD70741 ...
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Clock input timing Parameter External clock cycle External clock high-level width External clock low-level width External clock rise time External clock fall time 6 2 (input) 0.8 V (2) CLKOUT output timing Parameter CLKOUT cycle CLKOUT high-level ...
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Reset input timing Parameter Reset input width RESET (input) 68 Symbol Conditions MIN. t Power-on reset 10 15 WRL STOP mode 10 release System reset 30 15 PD70741 MAX. Unit CYK ...
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PD70741 69 ...
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SRAM, ROM, and I/O access timing (a) Access timing (1/2) Parameter Address output delay (relative to CLKOUT ) Address output hold time (relative to CLKOUT ) CSn output delay (relative to CLKOUT ) CSn output hold time (relative to ...
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Access timing (2/2) CLKOUT (output) 16 Note 18 CS0-CS3 (output) IORD, MRD (output) IOWR, UMWR, LMWR (output) READY (input) D0-D15 (input/output) (ADC = 0) (write) D0-D15 (input/output) (ADC = 1) (write) Note A0-A23 (output), UBE (output), BLOCK (output) Remark ...
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Read timing (1/2) Parameter Read cycle time Address access time Hold time from address to data input CSn access time Hold time from CSn to data input Delay from CSn to write data output (ADC = 0) Delay from ...
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Read timing (2/2) CLKOUT (output) A0-A23, UBE (output) CS0-CS3 (output) IORD, MRD (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance ...
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Write timing (1/2) Parameter Write cycle time CSn setup time (relative Address setup time (relative Address valid time prior to WR Address valid time after WR CSn valid time prior to WR CSn ...
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Write timing (2/2) CLKOUT (output) A0-A23, UBE (output) CS0-CS3 (output) IOWR, UMWR, LMWR (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance ...
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DRAM access timing (when DRAM is directly connected) (a) Read timing (normal access: off-page) (1/2) Parameter Delay from RD to write data output (ADC = 0) Delay from RD to write data output (ADC = 1) Read/write cycle time ...
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Read timing (normal access: off-page) (2/2) T1 CLKOUT (output) A0-A23, UBE COL. (output) RAS (output) UCAS, LCAS (output) WE (output) MRD (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. T2 ...
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Write timing (normal access: off-page) (1/2) Parameter Read/write cycle time RAS precharge time RAS pulse width RAS column address delay CAS hold width RAS-CAS precharge time Row address setup time Row address hold time Column address read time relative ...
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Write timing (normal access: off-page) (2/2) T1 CLKOUT (output) A0-A23, UBE COL. (output) RAS (output) UCAS, LCAS (output) WE (output) MRD (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. T2 ...
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READY input timing (normal access) Parameter READY setup time (relative to CLKOUT ) READY hold time (relative to CLKOUT ) CLKOUT (output) UCAS, LCAS (output) (read) UCAS, LCAS (output) (write) READY (input) 80 Symbol Conditions MIN ...
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PD70741 81 ...
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Read timing (high-speed page access: on-page) (1/2) Parameter Delay from RD to write data output (ADC = 0) Delay from RD to write data output (ADC = 1) CAS access time Access time from column address Output enable access ...
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Read timing (high-speed page access: on-page) (2/2) CLKOUT (output) A0-A23, UBE (output) RAS (output) UCAS, LCAS (output) WE (output) MRD (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance ...
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Write timing (high-speed page access: on-page) (1/2) Parameter CAS precharge time RAS hold width (write) CAS pulse width (write) Column address setup time (write) Column address hold time (write) Write command hold time Write command read time relative to ...
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Write timing (high-speed page access: on-page) (2/2) T1 CLKOUT (output) A0-A23, UBE (output) RAS (output) UCAS, LCAS (output) WE (output) MRD (output) D0-D15 (input/output) Notes 1. When ADC = 1 and other than DRAM access was performed in the ...
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DRAM access timing (when a control circuit is configured using a gate array or other devices) (a) Read timing (normal access: off-page) (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT ) RAS ...
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Read timing (normal access: off-page) (2/2) T1 CLKOUT (output) 96 A0-A23, UBE COL. (output) 99 RAS (output) UCAS, LCAS (output) WE (output) 102 MRD (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate ...
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Write timing (normal access: off-page) (1/2) Parameter Address output delay (relative to CLKOUT ) Address output hold time (relative to CLKOUT ) RAS output delay (relative to CLKOUT ) RAS output hold time (relative to CLKOUT ) CAS output ...
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Write timing (normal access: off-page) (2/2) T1 CLKOUT (output) 96 A0-A23, UBE COL. (output) 99 RAS (output) UCAS, LCAS (output) 106 WE (output) MRD (output) 108 D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines ...
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READY input timing (normal access) Parameter READY setup time (relative to CLKOUT ) READY hold time (relative to CLKOUT ) CLKOUT (output) UCAS, LCAS (output) (read) UCAS, LCAS (output) (write) READY (input) 90 Symbol Conditions MIN ...
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PD70741 91 ...
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Read timing (high-speed page access: on-page) (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT ) CAS output delay (relative to CLKOUT ) CAS output hold time (relative to CLKOUT ) MRD output ...
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Read timing (high-speed page access: on-page) (2/2) CLKOUT (output) 96 A0-A23, UBE (output) RAS (output) UCAS, LCAS (output) WE (output) MRD (output) D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. T1 ...
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Write timing (high-speed page access: on-page) (1/2) Parameter Address output delay (relative to CLKOUT ) Address output hold time (relative to CLKOUT ) CAS output delay (relative to CLKOUT ) CAS output hold time (relative to CLKOUT ) WE ...
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Write timing (high-speed page access: on-page) (2/2) T1 CLKOUT (output) 96 A0-A23, UBE (output) RAS (output) UCAS, LCAS (output) 106 WE (output) MRD (output) D0-D15 (input/output) Notes 1. When ADC = 1 and other than DRAM access was performed ...
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DRAM, CBR refresh timing Parameter READY setup time (relative to CLKOUT ) READY hold time (relative to CLKOUT ) RAS pulse width CAS setup time CAS hold time Refresh pulse width RAS precharge to CAS hold time REFRQ active ...
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DRAM, CBR self-refresh timing Parameter CAS setup time REFRQ active delay (relative to CLKOUT ) REFRQ inactive delay (relative to CLKOUT ) CAS hold time RAS precharge time Remark T: t CYK TI CLKOUT (output) REFRQ (output) RAS (output) ...
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Page-ROM access timing (1/2) Parameter Hold time from address to data input Hold time from CSn to data input Hold time from RD to data input Off-page address access time On-page address access time Off-page CSn access time Off-page ...
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Page-ROM access timing (2/2) T1 CLKOUT (output) A3-A23 Note 1 (output) A0-A2 Note 2 (output) CS3 (output) MRD (output) D0-D15 (input/output) Notes 1. The address pins to be used vary with the settings of bits MA5 to MA3 of ...
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Bus hold timing (1/2) Parameter HLDRQ setup time (relative to CLKOUT ) HLDRQ hold time (relative to CLKOUT ) HLDAK output delay (relative to CLKOUT ) HLDAK output hold time (relative to CLKOUT ) Delay from address float to ...
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Bus hold timing (2/ CLKOUT (output) 122 HLDRQ (input) HLDAK (output) A0-A23 (output) Note 2 MRD (output) CS3 (output) RAS (output) D0-D15 (input/output) Notes 1. The level existing immediately before the high-impedance state is held internally. 2. ...
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DMAC timing (1/2) Parameter DREQn setup time (relative to CLKOUT ) DREQn hold time (relative to CLKOUT ) DACKn output delay (relative to CLKOUT ) DACKn output hold time (relative to CLKOUT ) TC output delay (relative to CLKOUT ...
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DMAC timing (2/2) CLKOUT (output) 130 131 DREQ0, DREQ1 (input) DACK0, DACK1 (output) A0-A23, UBE (output) MRD, IORD (output) LMWR/WE, UMWR, IOWR (output) LCAS, UCAS (output) (read) LCAS, UCAS (output) (write) TC (output 132 137 ...
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INTPn input setup time, hold time Parameter INTPn input low setup time INTPn input high setup time INTPn input low pulse width INTPn input high-level width CLKOUT (output) INTPn (input) (edge mode) INTPn (input) (level mode) (13) NMI input ...
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RPU block timing Parameter Timer clock cycle time Timer clock high-level width Timer clock low-level width Timer clear cycle time Timer clear high-level width Timer clear low-level width Timer output high-level width Timer output low-level width Remark T: t ...
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CSI timing (a) Master mode Parameter Serial clock cycle time Serial clock high-level width Serial clock low-level width SI setup time (relative to SCLK ) SI hold time (relative to SCLK ) SO output delay (relative to SCLK ) ...
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PACKAGE DRAWINGS 100 PIN PLASTIC LQFP (FINE PITCH) (14 14 100 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. A ...
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RECOMMENDED SOLDERING CONDITIONS The PD70741 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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PD70741 111 ...
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The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V810, V821, and V810 Family are trademarks of NEC Corporation. No part of this document may be copied or reproduced in ...