MC68HC705P9CP Motorola, MC68HC705P9CP Datasheet
MC68HC705P9CP
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MC68HC705P9CP Summary of contents
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MC68HC705P9 HCMOS Microcontroller Unit TECHNICAL DATA MC68HC705P9/D REV. 3 ...
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CSIC MICROCONTROLLERS ...
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... Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Central Processor Unit (CPU Resets and Interrupts Low-Power Modes Parallel I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . 71 Computer Operating Properly Watchdog (COP Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Serial Input/Output Port (SIOP 107 Analog-to-Digital Converter (ADC 121 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Literature Updates . . . . . . . . . . . . . . . . . . . . . . . 151 Motorola, Inc., 1996 MOTOROLA List of Sections 3 ...
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... List of Sections List of Modules All M68HC05 microcontroller units (MCUs) are customer-specified modular designs. To meet customer requirements, Motorola is constantly designing new modules and new versions of existing modules. The following table shows the version levels of the modules in the MC68HC705P9 MCU. Central Processor Unit (CPU) ...
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... Revision History Introduction Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12 Programmable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Pin Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin Functions .15 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 RAM .24 EPROM/OTPROM .25 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 CPU Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 MOTOROLA Table of Contents Table of Contents 5 ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Interrupts Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Low-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Low-Power Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Parallel I/O Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Port .73 Port .76 Port .79 Port .82 COP Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Operation .86 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Low-Power Modes .88 6 Table of Contents MOTOROLA ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 Operation .110 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Low-Power Modes .120 ADC Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Operation .123 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Timing and Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . .125 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Low-Power Modes .130 MOTOROLA Table of Contents Table of Contents 7 ...
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... Literature Updates Literature Distribution Centers .151 Mfax .152 Motorola SPS World Marketing World Wide Web Server . . . . . . . . .152 CSIC Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . .152 8 Table of Contents ...
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... Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12 Programmable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1-mc68hc705p9 MOTOROLA Introduction Introduction 9 ...
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... Bytes of Page Zero EPROM/OTPROM – Eight Locations for User Vectors • 128 Bytes of User RAM • Bootloader ROM • Memory-Mapped Input/Output (I/O) Registers • Fully Static Operation with No Minimum Clock Speed • Power-Saving Stop, Wait, and Data-Retention Modes 10 Features Introduction 2-mc68hc705p9 MOTOROLA ...
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... PROGRAM COUNTER OSC1 INTERNAL OSCILLATOR OSC2 COP WATCHDOG V DD POWER V SS Figure 1. MC68HC705P9 Block Diagram 3-mc68hc705p9 MOTOROLA ARITHMETIC/LOGIC UNIT ACCUMULATOR INDEX REGISTER STACK POINTER CONDITION CODE REGISTER CPU CLOCK TO ADC INTERNAL CLOCK DIVIDE AND BY 2 SIOP DIVIDE ...
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... Table 2. Programmable Options Feature Enabled or Disabled Negative-Edge Triggering Only or Negative-Edge and Low-Level Triggering MSB First or LSB First Introduction Order Number MC68HC705P9P MC68HC705P9CP MC68HC705P9VP MC68HC705P9MP MC68HC705P9DW MC68HC705P9CDW MC68HC705P9VDW MC68HC705P9MDW MC68HC705P9S MC68HC705P9CS MC68HC705P9VS MC68HC705P9MS Option 4-mc68hc705p9 MOTOROLA ...
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... Contents Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Pin Functions . OSC1 and OSC2 .15 Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Ceramic Resonator Connections . . . . . . . . . . . . . . . . . . . . . . . .16 External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 IRQ/V PA7–PA0 .17 PB7/SCK–PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 PC7/V PD7/TCAP and PD5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1-mc68hc705p9 MOTOROLA and . .17 PP –PC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 RH Pin Descriptions Pin Descriptions 13 ...
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... Pin Descriptions Pin Assignments RESET IRQ/V PP PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5/SDO PB6/SDI PB7/SCK Pin Assignments Figure 1. Pin Assignments Pin Descriptions V DD OSC1 OSC2 PD7/TCAP TCMP PD5 PC0 PC1 PC2 PC3/AN3 PC4/AN2 PC5/AN1 PC6/AN0 PC7/V RH 2-mc68hc705p9 MOTOROLA ...
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... The frequency of the on-chip oscillator is f internal oscillator output by two to produce the internal clock with a frequency of f 3-mc68hc705p9 MOTOROLA and V are the power supply and ground pins. The MCU operates SS shows. Place the Crystal Ceramic resonator External clock signal ...
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... To minimize output distortion, mount the resonator and capacitors as close as possible to the pins. 16 Pin Functions Figure 3 shows a Figure 3. Crystal Connections shows a ceramic Figure 4. Ceramic Resonator Pin Descriptions MCU 10 M XTAL MCU CERAMIC RESONATOR Connections 4-mc68hc705p9 MOTOROLA ...
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... Port 8-pin bidirectional I/O port that shares five of its pins with the RH ADC. Use data direction register C to configure port C pins as inputs or outputs. 5-mc68hc705p9 MOTOROLA shows. pin has the following functions: PP Applying asynchronous external interrupt signals Applying V , the EPROM/OTPROM programming voltage ...
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... Port 2-pin I/O port that shares one of its pins with the capture/compare timer. Use data direction register D to configure port D pins as inputs or outputs. TCMP The TCMP pin is the output compare pin for the capture/compare timer. 18 Pin Functions Pin Descriptions 6-mc68hc705p9 MOTOROLA ...
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... EPROM/OTPROM .25 EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . .26 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . .26 Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Features • 2104 Bytes of EPROM/OTPROM – 48 Bytes of Page Zero EPROM/OTPROM – Eight Locations for User Vectors • 128 Bytes of User RAM • Bootloader ROM 1-mc68hc705p9 MOTOROLA Memory Memory 19 ...
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... Reserved $001F $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF 2-mc68hc705p9 MOTOROLA ...
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... Port D Data Register (PORTD) $0003 Data Direction Register A (DDRA) $0004 Data Direction Register B (DDRB) $0005 Data Direction Register C (DDRC) $0006 Data Direction Register D (DDRD) $0007 Unimplemented $0008 Unimplemented $0009 3-mc68hc705p9 MOTOROLA R/W Bit 7 6 Read: PA7 PA6 PA5 Write: Reset: Read: PB7 PB6 PB5 Write: ...
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... Write: Reset: Unaffected by reset = Unimplemented Memory Bit Bit IEDG OLVL Bit Bit Bit Reserved U = Unaffected 4-mc68hc705p9 MOTOROLA ...
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... Alternate Timer Register High (ATRH) $001A Alternate Timer Register Low (ATRL) $001B EPROM Programming Register (EPROG) $001C ADC Data Register (ADDR) $001D ADC Status/Control Register (ADSCR) $001E $001F Figure 2. I/O Register Summary (Continued) 5-mc68hc705p9 MOTOROLA R/W Bit 7 6 Read: Bit 7 6 Write: Reset: Read: Bit 15 14 Write: ...
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... The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 24 RAM R/W Bit Read Write: Reset: Unaffected by reset Read Write: Reset: Unaffected by reset = Unimplemented Memory Bit 0 0 SIOP IRQ COPE COPC R = Reserved U = Unaffected 6-mc68hc705p9 MOTOROLA ...
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... The following addresses are user EPROM/OTPROM locations: • • • The mask option register (MOR EPROM/OTPROM location at address $0900. 7-mc68hc705p9 MOTOROLA $0020–$004F $0100–$08FF $1FF8–$1FFF (reserved for user-defined interrupt and reset vectors) Memory Memory EPROM/OTPROM ...
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... Resets clear the EPGM bit EPROM/OTPROM programming power switched EPROM/OTPROM programming power switched off 26 EPROM/OTPROM Figure 3. EPROM Programming Register (EPROG) programming Memory Bit LATCH EPGM pin to the PP 8-mc68hc705p9 MOTOROLA ...
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... EPROM. Operation is fastest when unused external EPROM addresses contain $00. The bootloader function begins when a rising edge occurs on the RESETpin while the V logic one. 9-mc68hc705p9 MOTOROLA PP voltage. $0020–$004F $0100–$0900 $1FF0–$1FFF ...
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... A12 PB5 RESET PD7 PC5/AN1 PC1 20 PC2 V DD PC6/AN0 PB7/SCK 18 PC4 19 PC3 PB6/SDI Figure 4. Bootloader Circuit Memory MC14040B Q10 A10 Q11 Q12 A11 RST CLK S2 S3 10-mc68hc705p9 MOTOROLA ...
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... Select the bootloader function: 5. Close switch S1. 6. Turn on the V CAUTION: Turn on the V 7. Turn on the V 8. Open switch S1. The bootloader code begins to execute. If the 9. Close switch S1. 10. Turn off the V 11-mc68hc705p9 MOTOROLA Table 1 shows. Table 1. Bootloader Function Selection PC4/AN2 PC3/AN3 ...
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... Cerdip packages have a transparent window for erasing the EPROM with ultraviolet light. In the windowless PDIP and SOIC packages, the 2104 EPROM bytes function as one-time programmable ROM (OTPROM). 30 EPROM/OTPROM power supply before turning off the V PP power supply ultraviolet light with a wavelength of 2537 Memory power supply. DD 12-mc68hc705p9 MOTOROLA ...
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... The SIOP bit controls the shift direction into and out of the SIOP shift register. IRQ — Interrupt Request The IRQ bit makes the external interrupt function of the IRQ/V level-triggered as well as edge-triggered. 13-mc68hc705p9 MOTOROLA LSB first or MSB first SIOP data transfer Edge-triggered or edge- and level-triggered external interrupt pin Enabled or disabled COP watchdog Bit 7 6 ...
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... COPE enables the COP watchdog. In applications that have wait cycles longer than the COP watchdog timeout period, the COP watchdog can be disabled by not programming the COPE bit to logic one COP watchdog enabled 0 = COP watchdog disabled 32 Mask Option Register Memory 14-mc68hc705p9 MOTOROLA ...
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... Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .43 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . .44 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 1-hc05cpu MOTOROLA Central Processor Unit CPU CPU 33 ...
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... The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the instructions. The CPU registers contain data, addresses, and status bits that reflect the results of CPU operations. 34 Features CPU 2-hc05cpu MOTOROLA ...
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... MOTOROLA CPU CONTROL UNIT HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Figure 1. CPU Programming Model ...
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... CPU Registers The M68HC05 CPU contains five registers that control and monitor MCU operation: • Accumulator • Index register • Stack pointer • Program counter • Condition code register CPU registers are not memory mapped. 36 CPU Control Unit CPU 4-hc05cpu MOTOROLA ...
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... During a reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked. Read: Write: Reset: 5-hc05cpu MOTOROLA Bit Unaffected by reset Figure 2. Accumulator (A) Bit 7 6 ...
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... Loaded with vector from $1FFE and $1FFF Figure 5. Program Counter (PC Unimplemented Figure 6. Condition Code Register (CCR) CPU Bit Bit Unaffected 6-hc05cpu MOTOROLA 0 ...
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... C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. 7-hc05cpu MOTOROLA CPU CPU CPU Registers 39 ...
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... Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 40 Instruction Set CPU 8-hc05cpu MOTOROLA ...
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... The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. ...
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... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. ...
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... These instructions operate on CPU registers and memory locations. Memory Most of them use two operands. One operand is in either the Instructions accumulator or the index register. The CPU finds the other operand in memory. 11-hc05cpu MOTOROLA Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions Table 1. Register/Memory Instructions ...
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... Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence be- cause it does not write a replacement value. CPU Mnemonic ASL ASR (1) BCLR (1) BSET CLR COM DEC INC LSL LSR NEG ROL ROR (2) TST 12-hc05cpu MOTOROLA ...
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... The span of branching is from –128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. 13-hc05cpu MOTOROLA CPU CPU Instruction Set 45 ...
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... Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine CPU Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR 14-hc05cpu MOTOROLA ...
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... CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Control These instructions act on CPU registers and control CPU operation Instructions during program execution. 15-hc05cpu MOTOROLA Table 4. Bit Manipulation Instructions Instruction Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set Table 5 ...
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... DIR (b4 DIR (b5 DIR (b6 DIR (b7 — — — — — REL — — — — — REL — — — — — REL — — — — — REL 16-hc05cpu MOTOROLA ...
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... BRA rel Branch Always BRCLR n opr rel Branch if Bit n Clear BRN rel Branch Never BRSET n opr rel Branch if Bit n Set BSET n opr Set Bit n 17-hc05cpu MOTOROLA Effect on CCR Description (PC rel ? — — — — — PC (PC rel ? — ...
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... INH 5A 3 IX1 IMM DIR EXT — — — IX2 IX1 DIR INH 4C 3 — — — INH 5C 3 IX1 18-hc05cpu MOTOROLA ...
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... NEG ,X NOP No Operation ORA # opr ORA opr ORA opr Logical OR Accumulator with Memory ORA opr ,X ORA opr ,X ORA ,X 19-hc05cpu MOTOROLA Effect on CCR Description Jump Address — — — — — PC (PC Push (PCL); SP (SP) – 1 — ...
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... — 0 — — — INH 8E 2 DIR EXT — — — IX2 IX1 IMM DIR EXT — — IX2 IX1 20-hc05cpu MOTOROLA ...
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... Indexed, no offset addressing mode IX1 Indexed, 8-bit offset addressing mode IX2 Indexed, 16-bit offset addressing mode M Memory location N Negative flag n Any bit 21-hc05cpu MOTOROLA Effect on Description (PC Push (PCL) SP (SP) – 1; Push (PCH) SP (SP) – 1; Push (X) SP (SP) – 1; Push (A) — ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
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... Contents Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Low-Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 1-mc68hc705p9 MOTOROLA Resets and Interrupts Resets and Interrupts 55 ...
Page 56
... OPTION) RESET INTERNAL CLOCK Figure 1. Reset Sources pin generates a power-on reset. DD (internal clock cycle) delay after the oscillator becomes CYC , the MCU remains in the reset condition until CYC Resets and Interrupts RST S TO CPU AND D Q SUBSYSTEMS CK RESET LATCH 2-mc68hc705p9 MOTOROLA ...
Page 57
... ADDRESS BUS NOTES: 1. Internal clock, internal address bus, and internal data bus are not available externally. 2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence. RESET Pulse Width 3-mc68hc705p9 MOTOROLA V DD (NOTE 1) OSC1 PIN INTERNAL ...
Page 58
... RESET pin low when it detects a low-power supply voltage. The undervoltage sensing circuit may be made of discrete components or an integrated circuit can be used. For information about brownout and the COP watchdog, see the Computer Operating Properly Watchdog 58 Low-Voltage Protection Resets and Interrupts DD section. 4-mc68hc705p9 MOTOROLA ...
Page 59
... The CPU clears the IRQ latch during interrupt processing, so that another interrupt signal on the IRQ/V request during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. 5-mc68hc705p9 MOTOROLA SWI instruction IRQ/V pin PP Capture/compare timer ...
Page 60
... PP pin. An external interrupt request, shown in t ILIL t PIN ILIH PP t IRQ ILIH IRQ n Figure 5. External Interrupt Timing Resets and Interrupts (FROM CCR) EXTERNAL I INTERRUPT REQUEST RESET VECTOR FETCH pin is a programmable PP Figure 5, is latched pin low. PP 6-mc68hc705p9 MOTOROLA ...
Page 61
... An output compare interrupt request occurs if the output compare flag, Interrupt OCF, becomes set while the output compare interrupt enable bit, OCIE, is also set. OCF is in the timer status register, and OCIE is in the timer control register. 7-mc68hc705p9 MOTOROLA Table 2. External Interrupt Timing (V Characteristic = 5.0 Vdc 10 Vdc ...
Page 62
... The return from interrupt (RTI) instruction causes the CPU to recover the CPU registers from the stack as shown in 62 Interrupts Figure Resets and Interrupts 6. 8-mc68hc705p9 MOTOROLA ...
Page 63
... Function Reset Software Interrupt (SWI) External Interrupt Timer Interrupts 1. The COP watchdog is programmable in the mask option register. 9-mc68hc705p9 MOTOROLA UNSTACKING ORDER 5 1 CONDITION CODE REGISTER PROGRAM COUNTER (HIGH BYTE PROGRAM COUNTER (LOW BYTE) STACKING ORDER Figure 6. Interrupt Stacking Order Table 4 ...
Page 64
... I BIT SET? NO YES EXTERNAL CLEAR IRQ LATCH. INTERRUPT? NO TIMER YES INTERRUPT? STACK PC CCR. NO LOAD PC WITH INTERRUPT VECTOR. FETCH NEXT INSTRUCTION. SWI YES INSTRUCTION? NO RTI YES UNSTACK CCR PC. INSTRUCTION? NO EXECUTE INSTRUCTION. Figure 7. Interrupt Flowchart Resets and Interrupts SET I BIT. 10-mc68hc705p9 MOTOROLA ...
Page 65
... External reset — A logic zero on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. The timer begins counting from $FFFC. 1-mc68hc705p9 MOTOROLA Low-Power Modes pin loads the program counter with the PP Low-Power Modes pin — ...
Page 66
... Edge- and level-triggered external interrupt mask option 4. Reset vector shown as example 66 Stop Mode for stop recovery timing information ILIH 4064 t CYC 1FFE 1FFE 1FFE (NOTE 4) Figure 1. Stop Recovery Timing Low-Power Modes 1FFE 1FFE 1FFF RESET OR INTERRUPT VECTOR FETCH 2-mc68hc705p9 MOTOROLA ...
Page 67
... Figure 2 3-mc68hc705p9 MOTOROLA shows the sequence of events caused by the STOP instruction. STOP CLEAR I BIT IN CCR CLEAR TIMER INTERRUPT FLAGS AND TIMER INTERRUPT ENABLE BITS CLEAR TIMER PRESCALER TURN OFF OSCILLATOR NO RESET? YES EXTERNAL INTERRUPT? NO YES TURN ON OSCILLATOR DELAY 4064 CYCLES TO STABILIZE ...
Page 68
... MCU can periodically exit wait mode to reset the COP watchdog. • External reset — A logic zero on the RESET pin resets the MCU and loads the program counter with the contents of locations $1FFE and $1FFF. 68 Wait Mode Low-Power Modes pin PP 4-mc68hc705p9 MOTOROLA ...
Page 69
... Figure 3 5-mc68hc705p9 MOTOROLA shows the sequence of events caused by the WAIT instruction. WAIT CLEAR I BIT IN CCR STOP CPU CLOCK RESET? RESTART CPU CLOCK (1) FETCH RESET VECTOR OR (2) SERVICE INTERRUPT a. SAVE CPU REGISTERS ON STACK b. SET I BIT IN CCR c. VECTOR TO INTERRUPT SERVICE ROUTINE Figure 3. WAIT Instruction Flowchart ...
Page 70
... STOP and WAIT instructions on the WAIT STOP INTERNAL CLOCK 2 OSC1 INTERNAL OSCILLATOR OSC2 2 Figure 4. STOP/WAIT Clock Logic voltages as low as 2.0 Vdc. The data-retention DD voltage. The RESET pin must remain low DD to normal operating voltage. DD Low-Power Modes CPU CLOCK TIMER CLOCK ADC CLOCK 6-mc68hc705p9 MOTOROLA ...
Page 71
... Port A Data Register (PORTA .73 Data Direction Register A (DDRA .74 Port .76 Port B Data Register (PORTB .76 Data Direction Register B (DDRB .77 Port .79 Port C Data Register (PORTC .79 Data Direction Register C (DDRC .80 Port .82 Port D Data Register (PORTD .82 Data Direction Register D (DDRD .83 1-mc68hc705p9 MOTOROLA Parallel I/O Ports Parallel I/O Ports 71 ...
Page 72
... DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Write: Reset Read: 0 DDRB7 DDRB6 DDRB5 Write: Reset Unimplemented Parallel I/O Ports Bit 0 PA3 PA2 PA1 PA0 PC3 PC2 PC1 PC0 2-mc68hc705p9 MOTOROLA ...
Page 73
... Reset: PA[7:0] — Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. 3-mc68hc705p9 MOTOROLA R/W Bit Read: DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 ...
Page 74
... I/O logic of port A. READ DATA DIRECTION REGISTER A ($0004) WRITE DATA DIRECTION REGISTER A ($0004) RESET WRITE PORT A DATA REGISTER ($0000) READ PORT A DATA REGISTER ($0000) Figure 4. Port A I/O Circuit Parallel I/O Ports Bit 0 DDRA3 DDRA2 DDRA1 DDRA0 DDRAx PAx 4-mc68hc705p9 MOTOROLA PAx ...
Page 75
... When bit DDRAx is a logic zero, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. operation of the port A pins. 5-mc68hc705p9 MOTOROLA Table 1. Port A Pin Operation Data Direction Bit I/O Pin Mode (1) ...
Page 76
... When the SIOP is enabled, SCK is the SIOP clock output (in master mode) or the SIOP clock input (in slave mode). 76 Port B Bit PB7 PB6 PB5 Unaffected by reset SCK SDI SDO = Unimplemented Figure 5. Port B Data Register (PORTB) Parallel I/O Ports Bit 6-mc68hc705p9 MOTOROLA ...
Page 77
... These read/write bits control port B data direction. Reset clears DDRB[7:5], configuring all three port B pins as inputs. NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from Figure 7 7-mc68hc705p9 MOTOROLA Bit DDRB7 DDRB6 DDRB5 ...
Page 78
... Table 2. Port B Pin Operation Data Direction Bit I/O Pin Mode 0 Input, Hi-Z 1 Output 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input. Parallel I/O Ports DDRBx PBx Table 1 summarizes the Accesses to Data Bit Read Write (1) (2) Pin Latch Latch Latch 8-mc68hc705p9 MOTOROLA PBx ...
Page 79
... Unused analog inputs can be used as digital inputs, but pins PC3/AN3, PC4/AN2, PC5/AN1, and PC6/AN0 cannot be used as digital outputs while the ADC is on. Only pins PC0, PC1, and PC2 can be used as digital outputs when the ADC is on. 9-mc68hc705p9 MOTOROLA Bit PC7 PC6 ...
Page 80
... Writing to bits DDRC7–DDRC3 while the ADC is on can produce unpredictable ADC results. Figure 10 80 Port C Bit DDRC7 DDRC6 DDRC5 DDRC4 Figure 9. Data Direction Register C (DDRC) shows the I/O logic of port C. Parallel I/O Ports Bit 0 DDRC3 DDRC2 DDRC1 DDRC0 10-mc68hc705p9 MOTOROLA ...
Page 81
... The data latch can always be written, regardless of the state of its data direction bit. operation of the port C pins. 11-mc68hc705p9 MOTOROLA READ DATA DIRECTION REGISTER C ($0006) WRITE DATA DIRECTION REGISTER C ($0006) RESET WRITE PORT C DATA REGISTER ($0002) READ PORT C DATA REGISTER ($0002) Figure 10 ...
Page 82
... D. Reset has no effect on port D data. TCAP — Timer Capture TCAP is the input capture pin for the timer. 82 Port D Bit PD7 PD5 Unaffected by reset TCAP = Unimplemented Figure 11. Port D Data Register (PORTD) Parallel I/O Ports Bit 12-mc68hc705p9 MOTOROLA ...
Page 83
... Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from Figure 13 Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; a logic zero disables the output buffer. 13-mc68hc705p9 MOTOROLA Bit ...
Page 84
... D pins. 84 Port D Table 4. Port D Pin Operation Data Direction Bit I/O Pin Mode (1) 0 Input, Hi-Z 1 Output 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input. Parallel I/O Ports Table 1 summarizes the Accesses to Data Bit Read Write (2) Pin Latch Latch Latch 14-mc68hc705p9 MOTOROLA ...
Page 85
... COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Low-Power Modes .88 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Features • Protection from runaway software • 65.5-ms timeout period (with 2-MHz bus frequency) • Wait mode operation 1-cop0cop MOTOROLA COP COP 85 ...
Page 86
... For information about brownout protection, see the and Interrupts COP Watchdog Use the following formula to calculate the COP timeout period: Timeout Period where 86 Introduction section. 131 072 cycles COP Timeout Period = -------------------------------------- - crystal frequency f = -------------------------------------------- - BUS 2 COP Resets , f BUS 2-cop0cop MOTOROLA ...
Page 87
... EPROM location $1FF0 when read. $1FF0 Read: Write: Reset: COPC — COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 3-cop0cop MOTOROLA Bit ...
Page 88
... Wait Mode The COP watchdog continues to operate normally after a WAIT instruction. Software should periodically take the MCU out of wait mode and write to the COPC bit to prevent a COP watchdog timeout. 88 Low-Power Modes COP 4-cop0cop MOTOROLA ...
Page 89
... Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Alternate Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Low-Power Modes .106 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 1-tim1ic1oc_a MOTOROLA Timer Timer 89 ...
Page 90
... The timer provides a timing reference for MCU operations. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. structure of the timer module. 90 Features Timer Figure 1 shows the 2-tim1ic1oc_a MOTOROLA ...
Page 91
... EDGE SELECT/ TCAP DETECT LOGIC IEDG INTERNAL CLOCK (XTAL 2) 4 INTERNAL DATA BUS 3-tim1ic1oc_a MOTOROLA ICRH ICRL TRH TRL 16-BIT COUNTER 16-BIT COMPARATOR OCRH OCRL TIMER OVERFLOW OCIE OCF TOIE TOF ICIE ICF Figure 1. Timer Block Diagram Timer Introduction ATRH ATRL ...
Page 92
... Reset initializes ATRL to $FC = Unimplemented Timer Bit IEDG OLVL Bit Bit Bit Bit Bit Bit Bit Bit Unaffected 4-tim1ic1oc_a MOTOROLA ...
Page 93
... PD7/TCAP pin. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. the logic of the input capture function. 5-tim1ic1oc_a MOTOROLA 18 cycles. Timer resolution with a 4- Timer Timer ...
Page 94
... Figure 3. Input Capture Operation shows the logic of the output compare function. 16-BIT COUNTER 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) OCF OCIE Figure 4. Output Compare Operation Timer ICRL TRL TIMER INTERRUPT REQUEST PIN CONTROL TCMP LOGIC OLVL TIMER INTERRUPT REQUEST 6-tim1ic1oc_a MOTOROLA ...
Page 95
... A 2-bit prescaler in the timer is the limiting factor as it counts The minimum t Timer Resolution Input Capture Pulse Width Input Capture Pulse Period 2-bit prescaler in the timer is the limiting factor as it counts The minimum t 7-tim1ic1oc_a MOTOROLA Table 1. Timer Characteristics (V Characteristic (2) = 5.0 Vdc 10 unless otherwise noted. ...
Page 96
... Timing RESET T00 T01 T10 T11 16-BIT $FFFC Figure 6. Timer Reset Timing INTERNAL T00 T01 T10 T11 16-BIT $FFEB $FFEC COUNTER EDGE LATCH PREVIOUSLY CAPTURED VALUE FLAG Figure 7. Input Capture Timing Timer $FFFD $FFFE $FFFF $FFED $FFEE $FFEF $FFED 8-tim1ic1oc_a MOTOROLA ...
Page 97
... NOTES write to the output compare registers may occur at any time, but a compare only occurs at 2. The output compare flag is set at the timer state T11 that follows the comparison latch. TIMER CLOCKS 9-tim1ic1oc_a MOTOROLA INTERNAL BUS CLOCK T00 T01 TIMER T10 ...
Page 98
... Input capture registers (ICRH and ICRL) • Output compare registers (OCRH and OCRL) 98 Interrupts summarizes the timer interrupt sources. Table 3. Timer Interrupt Sources Global Source Local Mask Mask ICF Bit ICIE Bit OCF Bit OCIE Bit I Bit TOF Bit TOIE Bit Timer Priority (1 = Highest) 3 10-tim1ic1oc_a MOTOROLA ...
Page 99
... This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. Bits 4–2 — Unused These are read/write bits that always read as logic zeros. 11-tim1ic1oc_a MOTOROLA Enables input capture interrupts Enables output compare interrupts Enables timer overflow interrupts Controls the active edge polarity of the TCAP signal ...
Page 100
... OLVL bit to the TCMP pin • A timer rollover from $FFFF to $0000 $0013 Read: Write: Reset: 100 I/O Registers Bit ICF OCF TOF Unimplemented Figure 11. Timer Status Register (TSR) Timer Bit Unaffected 12-tim1ic1oc_a MOTOROLA ...
Page 101
... The TOF bit is automatically set when the 16-bit counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with TOF set, and then reading the low byte of the timer registers. Reset has no effect on TOF. 13-tim1ic1oc_a MOTOROLA 1 = Input capture input capture 1 = Output compare output compare ...
Page 102
... Reset initializes TRL to $FC = Unimplemented Figure 12. Timer Registers (TRH and TRL) INTERNAL DATA BUS LATCH READ TRH TRH ($0018) Figure 13. Timer Register Reads Timer Bit Bit Bit Bit 0 BUFFER TRL ($0019) 14-tim1ic1oc_a MOTOROLA ...
Page 103
... NOTE: To prevent interrupts between readings of ATRH and ATRL, set the interrupt mask (I bit) in the condition code register before reading ATRH, and clear the mask after reading ATRL. 15-tim1ic1oc_a MOTOROLA Bit Bit 15 14 ...
Page 104
... ICRL. 104 I/O Registers Bit Bit Unaffected by reset Bit Unaffected by reset = Unimplemented Figure 16. Input Capture Registers (ICRH and ICRL) Timer Bit Bit Bit 0 16-tim1ic1oc_a MOTOROLA ...
Page 105
... Disable interrupts by setting the I bit in the condition code register. 2. Write to OCRH. Compares are now inhibited until OCRL is written. 3. Clear bit OCF by reading the timer status register (TSR). 4. Enable the output compare function by writing to OCRL. 5. Enable interrupts by clearing the I bit in the condition code 17-tim1ic1oc_a MOTOROLA Bit Bit 15 14 ...
Page 106
... An input capture edge during stop mode sets the ICF bit and transfers the suspended timer counter value to the input capture registers. Wait Mode The timer remains active after a WAIT instruction. Any enabled timer interrupt request can bring the MCU out of wait mode. 106 Low-Power Modes Timer 18-tim1ic1oc_a MOTOROLA ...
Page 107
... PB5/SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 PB6/SDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Data Movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 SIOP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Low-Power Modes .120 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 1-siop_a MOTOROLA Serial Input/Output Port SIOP SIOP 107 ...
Page 108
... SIOP can increase the number of parallel I/O pins controlled by the MCU. More powerful peripherals such as analog-to-digital converters and real-time clocks are also compatible with the SIOP. Figure 1 108 Features shows the structure of the SIOP module. SIOP 4 4 2-siop_a MOTOROLA ...
Page 109
... FROM MOR SIOP CONTROL INTERNAL CLOCK (f 2) OSC Addr. Name $000A SIOP Control Register (SCR) $000B SIOP Status Register (SSR) $000C SIOP Data Register (SDR) 3-siop_a MOTOROLA INTERNAL BUS SIOP DATA REGISTER SIOP SPE MSTR SPIF DCOL DIVIDE ...
Page 110
... MCU ignores whatever it receives as a result of the transmission. The SIOP is simpler than the serial peripheral interface (SPI) on some other Motorola MCUs in that: • The polarity of the serial clock is fixed. ...
Page 111
... PB7/SCK pin is an output. The serial clock frequency in master mode is one-fourth the internal clock frequency. In slave mode, the PB7/SCK pin is an input. The maximum serial clock frequency in slave mode is one-fourth the internal clock rate. Slave mode has no minimum serial clock frequency. 5-siop_a MOTOROLA PB7/SCK PB6/SDI PB5/SDO SIOP SIOP ...
Page 112
... Operation shows the timing relationships among the serial clock, data SERIAL CLOCK SAMPLE INPUT DATA OUTPUT MSB BIT 6 BIT 5 DATA OUTPUT LSB BIT 1 BIT 2 Figure 3. SIOP Data/Clock Timing SIOP BIT 4 BIT 3 BIT 2 BIT 1 LSB BIT 3 BIT 4 BIT 5 BIT 6 MSB 6-siop_a MOTOROLA ...
Page 113
... SIOP data register on its PB5/SDO pin. At the same time, the slave MCU shifts out the contents of its SIOP data register on its PB5/SDO pin. master and slave exchange the contents of their data registers. 7-siop_a MOTOROLA , before the rising edge of the serial clock and S Table 1 and ...
Page 114
... Unit MHz ( ) SIOP M OSC OSC f dc 525 kHz ( ) SIOP S (2) t 4.0 4 SCK M CYC t — 1920 SCK S t 932 — ns SCKL t — 200 — 100 — 100 — unless otherwise noted 8-siop_a MOTOROLA LSB ...
Page 115
... SDO Hold Time SDI Setup Time SDI Hold Time CYC 3. f OSC 4. In master mode, the frequency of SCK is f Interrupts The SIOP does not generate interrupt requests. 9-siop_a MOTOROLA Table 2. SIOP Timing (V Characteristic = 1.0 MHz 3.3 Vdc 10 Vdc ...
Page 116
... The data direction register and the port data register remain in their SIOP-initialized state. NOTE: After clearing SPE, be sure to initialize the port for its intended I/O use. 116 I/O Registers Bit SPE 0 MSTR Figure 6. SIOP Control Register (SCR) SIOP Bit 10-siop_a MOTOROLA ...
Page 117
... MSTR initializes the PB7/SCK pin as the serial clock output. Clearing MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can be set at any time regardless of the state of SPE. Reset clears MSTR. 11-siop_a MOTOROLA 1 = SIOP enabled 0 = SIOP disabled 1 = Master mode selected 0 = Slave mode selected ...
Page 118
... SIOP status register while SPIF is set and then reading or writing the SIOP data register. Reset clears SPIF Transmission complete 0 = Transmission not complete 118 I/O Registers Bit SPIF DCOL Figure 7. SIOP Status Register (SSR) SIOP Bit 12-siop_a MOTOROLA ...
Page 119
... This register is not buffered. Writing to the SIOP data register overwrites the previous contents. Reading or writing to the SIOP data register while a transmission is in progress can cause invalid data to be transmitted or received. 13-siop_a MOTOROLA 1 = Invalid access of SDR 0 = Valid access of SDR Bit 7 6 ...
Page 120
... A STOP instruction in a master SIOP does not suspend the clock to slave SIOPs. Wait Mode The WAIT instruction suspends the clock to the SIOP. When the MCU exits wait mode, processing resumes immediately. A WAIT instruction in a master SIOP does not suspend the clock to slave SIOPs. 120 Low-Power Modes SIOP 14-siop_a MOTOROLA ...
Page 121
... ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Low-Power Modes .130 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Features • 8-Bit Conversions with • Four External and Three Internal Analog Input Channels • Wait Mode Operation 1-atd4x8nvrl MOTOROLA Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 RH 1.5-LSB Precision ADC ADC 121 ...
Page 122
... Introduction Figure 1 shows the structure of the ADC AN3 COMPARATOR AN2 INPUT MULTIPLEXER AN1 AN1 CH2 CH1 CH0 DIGITAL TO-ANALOG V CONVERTER SS CCF ADON CONTROL LOGIC INTERNAL CLOCK (XTAL 2) INTERNAL RC ADRC OSCILLATOR Figure 1. ADC Block Diagram ADC 2-atd4x8nvrl MOTOROLA ...
Page 123
... PC7/V The voltage reference high pin (PC7/V RH voltage for the ratiometric conversion process. For ratiometric conversion, the supply voltage of the analog source should be the same as V 3-atd4x8nvrl MOTOROLA Table 1. ADC I/O Register Summary R/W Bit 7 6 Read: Bit 7 6 Write: Reset: ...
Page 124
... ADRC bit to logic one in the ADC status and control register. Interrupts The ADC cannot generate interrupt requests. 124 Interrupts converts to digital $FF; an input RH converts to $FF with no overflow. An analog RH converts to digital $00. For ratiometric ADC as the RH 4-atd4x8nvrl MOTOROLA ...
Page 125
... ADC accuracy may decrease proportionately cycle time of the A/D converter AD 4. Source impedances more than 10 k sampling External system error caused by input leakage approximately equals R source times input current. 5-atd4x8nvrl MOTOROLA Table 2. ADC Characteristics (V Characteristic (2) > ...
Page 126
... ADC data register. Resets clear the CCF bit Conversion complete 0 = Conversion not complete 126 I/O Registers Bit CCF 0 ADRC ADON Unimplemented Figure 2. ADC Status and Control Register (ADSCR) ADC Bit 0 0 CH2 CH1 CH0 6-atd4x8nvrl MOTOROLA ...
Page 127
... Resets clear the ADON bit. Bits 4–2 — Not used Bits 4–2 always read as logic zeros. 7-atd4x8nvrl MOTOROLA 1 = Internal RC oscillator drives ADC 0 = Internal clock drives ADC Because of the frequency tolerance of the RC oscillator and its asynchronism with the internal clock, the conversion complete flag must be used to determine when a conversion sequence is complete ...
Page 128
... Reading a port pin that is selected as an analog input returns a logic zero. 128 I/O Registers Table 3. Channels 0–3 are the input pins, PC3/AN3, Table 3. ADC Input Channel Selection CH[2:1:0] Channel 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 ADC Signal AN0 AN1 AN2 AN3 Reserved 8-atd4x8nvrl MOTOROLA ...
Page 129
... ADC Data Register The ADC data register (ADDR read-only register that contains the result of the most recent analog-to-digital conversion. $001D Read: Write: Reset: 9-atd4x8nvrl MOTOROLA Bit Bit Unaffected by reset Figure 3. ADC Data Register (ADDR) ADC ...
Page 130
... If the ADC is not being used, clear both the ADON and ADRC bits before entering wait mode. • If the ADC is being used and the internal clock rate is above 1 MHz, clear the ADRC bit before entering wait mode. 130 Low-Power Modes ADC 10-atd4x8nvrl MOTOROLA ...
Page 131
... Maximum Supply Current vs. Internal Clock Frequency . . . . . . . . . .139 5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 3.3 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Test Load .142 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 28-Pin PDIP — Case #710 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 28-Pin Cerdip — Case #733 . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 28-Pin SOIC — Case #751F . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 1-mc68hc705p9 MOTOROLA Specifications Specifications 131 ...
Page 132
... Connect unused inputs to the appropriate IN OUT Table 1. Maximum Ratings Rating Symbol and STG 5 Electrical Characteristics on page 136 for guaranteed Specifications Value Unit –0 – 16.75 V –65 to +150 C on page 135 and 2-mc68hc705p9 MOTOROLA ...
Page 133
... V = Automotive temperature range (–40 to +105 Automotive temperature range (–40 to +125 C) Thermal Characteristics Thermal Resistance Plastic Dual In-Line Package (PDIP) Small Outline Integrated Circuit (SOIC) Ceramic Dual In-Line Package (Cerdip) 3-mc68hc705p9 MOTOROLA Table 2. Operating Temperature Range Package Type (1) (2) ( ...
Page 134
... --------------------------------- - 273 Using this value of K, the values Specifications , in C can be obtained from and T is approximately 273 (at equilibrium) for a D and T can be obtained 4-mc68hc705p9 MOTOROLA (1) (2) (3) ...
Page 135
... C 4. Wait mode and stop mode I measured with all ports configured as inputs Stop mode I measured with OSC1 = Wait mode I affected linearly by OSC2 capacitance DD 5-mc68hc705p9 MOTOROLA Symbol –PC0, PD5 –PC0, PD5, ...
Page 136
... V V — — 0 2.0 — — V — 1.6 2.3 mA — 0.9 1.3 mA — 0.4 0.6 mA — 1 — — — — — — — — — — — — 2.1 MHz); all inputs 0.2 V from OSC = 0 – 0 6-mc68hc705p9 MOTOROLA ...
Page 137
... Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances. Within the limited range of values shown curves are approximately straight lines 5.0 V, devices are specified and tested for 3.3 V, devices are specified and tested for V DD Figure 2. Typical Low-Side Driver Characteristics 7-mc68hc705p9 MOTOROLA = 5.0 V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 – ...
Page 138
... Figure 3. Typical Supply Current vs. Internal Clock Frequency 138 Typical Supply Current vs. Internal Clock Frequency 5.0 RUN MODE 25 C 5.5 V 4.0 4.5 V 3.6 V 3.0 3.0 V 2.0 1.0 0 0.5 1.0 1.5 0 INTERNAL CLOCK FREQUENCY (MHz) 1.2 WAIT MODE 1.0 ADC OFF 0.8 RUN MODE 0 ADC ON 5.5 V 0.4 4.5 V 3.6 V 0.2 3 1.5 2.0 0 INTERNAL CLOCK FREQUENCY (MHz) Specifications 2 5.5 V 4.5 V 3.6 V 3.0 V 0.5 1.0 1.5 2.0 8-mc68hc705p9 MOTOROLA ...
Page 139
... C 6.0 Run Mode Wait Mode (ADC On) Wait Mode (ADC Off) 5.0 4.0 3.0 2.0 1.0 0 0.5 0 INTERNAL CLOCK FREQUENCY (MHz) Figure 4. Maximum Supply Current vs. Internal Clock Frequency 9-mc68hc705p9 MOTOROLA Maximum Supply Current vs. Internal Clock Frequency 2.5 2.0 1.5 1.0 0.5 1.0 1.5 2.0 Specifications V = 3.3 V 10% DD –40 to +125 C Run Mode Wait Mode (ADC On) ...
Page 140
... OXOV t — 100 ms ILCH t 1.5 — CYC t 4.0 — t RESL CYC 125 — (3) t Note — t TLTL CYC t 125 — ns ILIH (4) t Note — t ILIL CYC — — RCON t — 100 s ADON CYC 10-mc68hc705p9 MOTOROLA ...
Page 141
... Input Capture Pulse Period Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width 2-bit prescaler in the timer is the limiting factor as it counts The minimum t 4. The minimum t 11-mc68hc705p9 MOTOROLA Table 7. Control Timing (V Characteristic OSC (2) = 3.3 Vdc 10%, V ...
Page 142
... Small outline integrated circuit (SOIC) The following figures show the latest packages at the time of this publication. To make sure that you have the latest package specifications, contact one of the following: • Local Motorola Sales Office • Motorola Mfax – Phone 602-244-6609 – EMAIL rmfax0@email.sps.mot.com • ...
Page 143
... PDIP — Case #710 28-Pin Cerdip — Case #733 28 1 -A- N -T- SEATING PLANE G H 13-mc68hc705p9 MOTOROLA 0.25 (0.010 Specifications Specifications Mechanical Specifications NOTES: 1. DIMENSIONS A AND B INCLUDES MENISCUS. ...
Page 144
... Specifications 28-Pin SOIC — Case #751F - 28X -T- G 26X 144 Mechanical Specifications 15 P 14X - - Specifications 14-mc68hc705p9 MOTOROLA ...
Page 145
... B bootloader ROM . . . . . . . . . . . . . . . . . . . . .26 bootload procedure . . . . . . . . . . . . . . . .29 bootloader circuit . . . . . . . . . . . . . . . . . .28 location . . . . . . . . . . . . . . . . . . . . . . . . .27 brownout . . . . . . . . . . . . . . . . . . . . . . . .58, 86 bypass capacitors . . . . . . . . . . . . . . . . . . . .15 MOTOROLA C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 case outlines . . . . . . . . . . . . . . .12, 143–144 CCF bit . . . . . . . . . . . . . . . . . . . . . . .124, central processor unit ceramic resonator circuit CH[2:0] bits . . . . . . . . . . . . . . . . . . . . . . .128 computer operating properly watchdog condition code register ...
Page 146
... ICF bit . . . . . . . . . . .61, 98, 101, 104, 106 . . . . . . .133 ICIE bit . . . . . . . . . . . . . . . . . . .61, 98–99 IEDG bit . . . . . . . . . . . . . . . . . . . . . . .100 Index . . . . . . . . . . . .133 . . . . . . . . . . . . . . . . . . .17, 59–60, 88, 106 . . . . . . . . . . . . . . . .57, 88, 106 .127, 130 . . . . . . . . . . . . . . . . . . . . . . .128 . . . . . . . . . . . . . . . . .58, 87– .26 MOTOROLA ...
Page 147
... ADC status and control register (ADSCR .124, 126 alternate timer registers (ATRH/L) COP register (COPR .58, 87 data direction register A (DDRA) MOTOROLA data direction register B (DDRB) data direction register C (DDRC) data direction register D (DDRD) EPROM programming register input capture registers input capture registers ...
Page 148
... I/O ports .12, 25, 31, 86 PB[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . .76 PB5/SDO pin Index . . . . . . . . . . . . . . . . . . . .56, 88, 120 . . . . . . . . . . . . . . . . . . . . . . . . . .133 . . . . . . . . . . . . . . . . . . . . .90 .94, 100–101, 105 . . .77, 111–112, 116 MOTOROLA ...
Page 149
... DD power supply ( .29 PP power-on reset . . . . . . . . . . . . . . . . . . . . . .56 program counter (PC .42, 45, 56, 62 MOTOROLA programmable options COP watchdog enable/disable external interrupt pin triggering SIOP data format quartz window RAM locations stack . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Reading . . . . . . . . . . . . . . . . . . . . . . . . . .102 registers ...
Page 150
... ADC effect on capture/compare timer . . . . . . . . . .67 effect on COP watchdog effect on SIOP STOP/WAIT clock logic WAIT instruction flowchart Index . . . . . . . . . . . . . . . . . . . . . . .61 .106 . . . . . . . . . . . . . . . . . . . . . . . . .61–62 . .100–102 . . . . . . . . . . . . . . . . . . . . . .61–62, 100, 104–105 .15 . .130 . . . . .106 . . . . . . . . . . . . .120 . . . . . . . . . . . . .69 MOTOROLA ...
Page 151
... Phone 1 800 441-2447 or 602 303-5454 Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC Toshikatsu Otsuki 6F Seibu-Butsuryu Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan Phone 03-3521-8315 Hong Kong: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong Phone 852-26629298 MOTOROLA Literature Updates Literature Updates 151 ...
Page 152
... Or, on the http://Design-NET.com home page, select the Mfax icon. Obtain a fax of complete, easy-to-use Mfax instructions by entering your FAX number and then pressing the 1 key. Motorola SPS World Marketing World Wide Web Server Use the Internet to access this World Wide Web Server. Use the following URL: http://Design-net.com CSIC Microcontroller Division’ ...
Page 153
Please help us to continue improving the quality and usefulness of our data books by filling out this form and sending your comments to us. You can return the form by mail, or FAX it to 512-891-3236. Thank you for ...
Page 154
... Second: fold back along this line Please supply the following information (optional). Name: __________________________________________________________________ Company Name: ________________________________________________________ Title: ____________________________________________________________________ Address: _________________________________________________________________ City: ____________________________________________State: _____Zip:__________ Phone Number: _________________________________________________________ Motorola 6501 William Cannon Drive West Mail Stop OE17 Austin, Texas 78735-8598 USA Attention: CSIC Publications Department PLEASE PASTE ...
Page 155
CSIC MICROCONTROLLERS ...
Page 156
... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its offi ...