MC14526B ON Semiconductor, MC14526B Datasheet

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MC14526B

Manufacturer Part Number
MC14526B
Description
Manufacturer
ON Semiconductor
Datasheet

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MC14526B
Presettable 4−Bit Down
Counters
and N−channel enhancement mode devices in a monolithic structure.
with a decoded “0” state output for divide−by−N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide−by−N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
synthesizers, phase−locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Features
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
(e.g., either V
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 5
MAXIMUM RATINGS
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation per Package (Note 1)
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
The MC14526B binary counter is constructed with MOS P−channel
This device is presettable, cascadable, synchronous down counter
This complementary MOS counter can be used in frequency
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level
Clock or Negative Transition of Inhibit
Schottky TTL Load Over the Rated Temperature Range
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Design: Incremented on Positive Transition of
Asynchronous Preset Enable
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Pb−Free Packages are Available*
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
SS
SS
or V
Rating
v (V
DD
in
). Unused outputs must be left open.
or V
out
) v V
DD
.
Symbol
I
in
V
V
V
T
P
, I
T
T
DD
out
stg
in
in
D
A
L
out
,
and V
−0.5 to V
out
−0.5 to +18.0
−55 to +125
−65 to +150
should be constrained
Value
±10
500
260
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
1
1
1
A
WL, L
YY, Y
WW, W = Work Week
G
ORDERING INFORMATION
SOIC−16 WB
DW SUFFIX
CASE 751G
SOEIAJ−16
CASE 648
CASE 966
P SUFFIX
F SUFFIX
http://onsemi.com
PDIP−16
= Assembly Location
= Wafer Lot
= Year
= Pb−Free Package
Publication Order Number:
1
1
1
MC14526BCP
AWLYYWWG
DIAGRAMS
AWLYWWG
MC14526B
MARKING
ALYWG
14526B
MC14526B/D

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MC14526B Summary of contents

Page 1

... MC14526B Presettable 4−Bit Down Counters The MC14526B binary counter is constructed with MOS P−channel and N−channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded “0” state output for divide−by−N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide− ...

Page 2

... Q0 is the LSB. V (Pin 8) — The most negative power supply potential. SS This pin is usually ground. V (Pin 16) — The most positive power supply potential may range from 3 with respect STATE DIAGRAM MC14526B http://onsemi ...

Page 3

... The formulas given are for the typical characteristics only at 25_C calculate total supply current at loads other than 50 pF (50 pF – 50) Vfk (per package), C where pF MC14526B ) SS V −55°C DD Vdc Symbol Min Max Min V 5.0 − 0.05 − ...

Page 4

... Preset Enable Pulse Width Reset Pulse Width Reset Removal Time 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. MC14526B ( pF 25_C) (Note 5) L ...

Page 5

... RESET C L INHIBIT C L 0" CLOCK PULSE GENERATOR 20 ns 90% CLOCK 50% 10% VARIABLE 50% DUTY CYCLE WIDTH Figure 3. Power Dissipation MC14526B POWER SUPPLY http://onsemi.com ...

Page 6

... TLH Figure 90% ANY P 50% 10% t PLH ANY Q 50% Figure 90% PRESET 50% ENABLE 10% t PHL 0" 50% Figure 9. MC14526B SWITCHING WAVEFORMS V DD 90% INHIBIT V SS 90% ANY Q 50% OR 0" 10% THL RESET V DD ANY PHL CLOCK ANY P DD GND ...

Page 7

... Clock pulse. The Inhibit pin may be used to stop pulse counting. When this pin is taken high, decrementing is inhibited. MC14526B MC14526B LOGIC DIAGRAM (Binary Down Counter ...

Page 8

... LOAD ORDERING INFORMATION Device MC14526BCP MC14526BCPG MC14526BDW MC14526BDWG MC14526BDWR2 MC14526BDWR2G MC14526BF MC14526BFG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MC14526B ...

Page 9

... B B 16X 0. SEATING e PLANE 14X T MC14526B PACKAGE DIMENSIONS PDIP−16 CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS 4. DIMENSION B DOES NOT INCLUDE 5. ROUNDED CORNERS OPTIONAL. L SEATING PLANE SOIC−16WB CASE 751G− ...

Page 10

... H 7.40 8.20 0.291 0.323 E L 0.50 0.85 0.020 0.033 L 1.10 1.50 0.043 0.059 0.70 0.90 0.028 0.035 1 Z −−− 0.78 −−− 0.031 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC14526B/D ...

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