UPD70433GD-12-5BB Renesas Electronics Corporation., UPD70433GD-12-5BB Datasheet
UPD70433GD-12-5BB
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UPD70433GD-12-5BB Summary of contents
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DESCRIPTION The PD70433 (V55PI microprocessor in which a 16-bit CPU, RAM, serial interface, parallel interface, A/D converter, timers, DMA controller, interrupt controller, etc., are integrated in a single chip. The V55PI is software-compatible with the PD70320 and 70330 ...
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Interrupt controller • Programmable priority (4 levels) • Three interrupt servicing methods Vectored interrupt function, register bank switching function, macro service function 16-bit timer: 4 channels Watchdog timer function Software interval timer (16 bits) Address field wait insertion function and ...
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PIN CONFIGURATION (TOP VIEW) (1) 120-Pin Plastic QFP (28 28 mm), 120-pin plastic QFP (fine pitch) (20 PD70433GD-xx-5BB PD70433GJ-xx-3EB 119 117 120 118 116 BUSLOCK 2 HLDAK 3 HLDRQ 4 READY 5 POLL 6 CLKOUT 7 RESET ...
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Ceramic PGA PD70433R-xx Bottom View Locator Pin Remark The locator pin is not included in the pin count. No. Signal Nane Port A1 ANI1 P61 A2 AV –– SS ...
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No. Signal Nane Port F1 RTPT7 P77 F2 RTPT6 P76 F3 RTPT4 P74 F12 ––– P07 F13 ––– P05 F14 ––– P04 G1 NC ––– G2 DMARQ0 P80 G3 V ––– DD G12 ––– P03 G13 ––– P02 G14 ––– ...
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EXU GENERAL V DD REGISTERS & GND ALU DATA MEMORY 512 BYTES MICRO SEQUENCE CONTROL MICRO ROM ASTB READY RD BCU DMA WRH PREFETCH request WRL QUEUE IORD 6 BYTES IOWR BUS RAS CONTROL DEX & D8/D16 PREFETCH CONTROL BUSLOCK ...
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PIN FUNCTIONS ....................................................................................................................................... 10 1.1 LIST OF PIN FUNCTION .................................................................................................................................... 10 1.1.1 Port Pins ................................................................................................................................................ 10 1.1.2 Non-Port Pins ........................................................................................................................................ 11 2. BLOCK CONFIGURATION ....................................................................................................................... 14 2.1 BUS CONTROL UNIT (BCU) ............................................................................................................................. 14 2.2 EXECUTION UNIT (EXU) ................................................................................................................................... 14 ...
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INTERRUPT FUNCTIONS ......................................................................................................................... 42 5.1 FEATURES ......................................................................................................................................................... 42 5.2 INTERRUPT RESPONSE METHODS ............................................................................................................... 45 5.2.1 Vectored Interrupts .............................................................................................................................. 45 5.2.2 Register Bank Switching Function .................................................................................................... 46 5.2.3 Macro Service Function ....................................................................................................................... 47 6. DMA FUNCTION (DMA CONTROLLER) ..................................................................................................48 6.1 ...
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SOFTWARE INTERVAL TIMER FUNCTION ........................................................................................... 70 15.1 SOFTWARE INTERVAL TIMER CONFIGURATION ........................................................................................ 70 16. CODEC INSTRUCTION.............................................................................................................................. 71 16.1 FEATURES .......................................................................................................................................................... 71 16.2 MEMORY MAP ................................................................................................................................................... 74 16.3 PROCESSING FLOW ......................................................................................................................................... 76 17. INSTRUCTION SET .................................................................................................................................... 78 17.1 INSTRUCTIONS NEWLY ...
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PIN FUNCTIONS 1.1 LIST OF PIN FUNCTIONS 1.1.1 Port Pins Pin Name Input/Output Port 0 P00 to P07 Input/output Input/output specifiable bit-wise 8-bit input/output port P10* P11 P12 Port 1 P13 Input 7-bit input port P14 P15 P16 P20 ...
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Non-Port Pins (1) Bus control pins Input/ Pin Name Output ASTB External bus cycle address strobe signal output in external bus External memory cycle data read strobe signal output in RD external bus Output External memory cycle lower byte ...
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Other pins Input/ Pin Name Output GND GND potential V Positive power supply DD ––– AV A/D converter GND potential SS AV A/D converter analog power supply DD AV A/D converter reference voltage input REF RESET Input System reset ...
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Input/ Pin Name Output SO0 Output CSI transmission data output SO1 SI0 Input CSI reception data input SI1 SCK0 CSI serial clock input/output SCK1 PD0 to PD7 Parallel interface — Data input/output Input/output DATASTB Parallel interface — Data strobe signal ...
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BLOCK CONFIGURATION 2.1 BUS CONTROL UNIT (BCU) The BCU performs control of the main bus. The BCU starts the necessary internal/external bus cycle on the basis of the physical address obtained from the execution unit (EXU). 2.2 EXECUTION UNIT ...
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CLOCK GENERATOR (CG) The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins and supplies it as the CPU operating clock. 2.14 ...
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CPU FUNCTIONS The CPU of the V55PI is software upword compatible with the V20 and V30 (native mode), and the V25 and V35. 3.1 FEATURES Software upward compatible with V20 & V30 (native mode) and V25 & V35 (includes ...
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REGISTERS The V55PI CPU has general register sets compatible with the V20 and V30 (native mode), and the V25 and V35. The general register sets are mapped onto the register file space. These general register sets are also used ...
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Figure 3-1. Register Bank Configuration 000H Register Bank 0 020H 1 040H 2 060H 3 080H 4 0A0H 5 0C0H 6 0E0H 7 100H 8 120H 9 140H 10 160H 11 180H 12 1A0H 13 1C0H 14 1E0H 15 1FFH ...
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General Registers (AW, BW, CW, DW) There are four 16-bit general registers. In addition to being accessed as 16-bit registers, these registers can also be accessed as 8-bit registers by dividing each register into upper and lower 8-bit halves ...
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Pointers (SP, BP) and Index Registers (IX, IY) These are 16-bit registers used as base pointers or index registers in memory accesses using based addressing (BP), indexed addressing (IX, IY), based indexed addressing (BP, IX, IY), etc. The SP ...
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However, using a segment override prefix instruction makes it possible for access of general variables to change from DS0 to another segment register. Also, in addressing which uses BP as the base register, another segment register can be used instead ...
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Extended Segment Register 8-Bit Fixed When a reset is performed, DS2 and DS3 of register bank 15 are initialized to 0000H. ...
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PROGRAM COUNTER (PC) This is a 16-bit binary counter which holds the offset value of the program memory address on which the CPU is to perform execution. The PC is incremented each time an instruction code is fetched from ...
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MEMORY SPACE The V55PI has a 16M-byte memory space. Of this, using lowest 1M bytes (000000H to 0FFFFFH) as the basic memory space, the 16M bytes including the basic memory space (000000H to FFFFFFH) can be accessed as the ...
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H 1M Bytes 0FFF0H to 0FFFFFH is a program area used for the system boot, and PS and PC become 0FFFH and 0H, respectively, therefore the program ...
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3.5.3 Special Function Register Area The 496-byte space 0FFE00H to 0FFFEFH has ...
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Address Special Function Register Name 0FFE00H A/D conversion result register 0 0FFE02H A/D conversion result register 1 0FFE04H A/D conversion result register 2 0FFE06H A/D conversion result register 3 0FFE10H Parallel interface buffer 0FFE18H Parallel interface control register 0 0FFE19H ...
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Address Special Function Register Name 0FFECEH Interrupt request control register 14 0FFED0H Interrupt request control register 16 0FFED1H Interrupt request control register 17 0FFED2H Interrupt request control register 18 0FFED3H Interrupt request control register 19 0FFED4H Interrupt request control register ...
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Address Special Function Register Name 0FFF04H Port 4 0FFF05H Port 5 0FFF06H Port 6 0FFF07H Port 7 0FFF08H Port 8 0FFF0CH Port read control register 0FFF0EH Real–time output port 0FFF10H Port 0 mode register 0FFF12H Port 2 mode register 0FFF13H ...
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Address Special Function Register Name 0FFF30H Timer control register 0 0FFF31H Timer control register 1 0FFF32H Timer output control register 0 0FFF33H Timer output control register 1 0FFF34H External interrupt mode register 0 0FFF35H External interrupt mode register 1 0FFF40H ...
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Address Special Function Register Name 0FFF66H Timer compare register 31 0FFF6CH PWM register 0FFF6DH PWM control register 0FFF70H Transmit baud rate generator register 0 0FFF71H Receive baud rate generator register 0 0FFF72H Prescaler register 0 0FFF73H UART mode register 0 ...
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Address Special Function Register Name 0FFF84H Terminal counter modulo register 0 (low) 0FFF86H Terminal counter modulo register 0 (high) 0FFF88H DMA up/down counter 0 (low) 0FFF8AH DMA up/down counter 0 (high) 0FFF8CH DMA compare register 0 (low) 0FFF8EH DMA compare ...
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Address Special Function Register Name 0FFFB4H DMA read/write pointer 1 (low) 0FFFB6H DMA read/write pointer 1 (high) 0FFFBCH DMA mode register 1 0FFFBDH DMA control register 1 0FFFE0H Software timer/counter 0FFFE2H Software timer/counter compare register 0FFFE8H Programmable wait control register ...
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Vector Table Area The 1K–byte area 00000H to 003FFH in the memory space holds 256 vectors (4 bytes used per vector) for the start addresses of interrupt routines initiated by interrupt requests, break instructions, etc. In the initial state, ...
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Vector 40 (000A0H) : System reserved Vector 41 (000A4H) : System reserved Vector 42 (000A8H) : System reserved Vector 43 (000ACH) : System reserved Vector 44 (000B0H) : System reserved Vector 45 (000B4H) : System reserved Vector 46 (000B8H) : ...
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REGISTER FILE SPACE The register file space is shown in Figure 3-5. The size of the register file space is 512 bytes, and a maximum 16-bank register set can be set. The register file space is separate from the ...
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Macro Service Work Area Macro Service Control Word Area Register Bank Macro Service Channel Area ...
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I/O SPACE The V55PI has a 64K-byte I/O space. The I/O space map is shown in Figure 3-6. The I/O space is accessed using address bus/data bus and control signals (IORD, IOWR, etc output from the unused ...
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BUS CONTROL FUNCTIONS With the V55PI pin, refer to 1.1.2 (1) "Pin function for bus control". As regards pins which have an alternate function as port pins, when that function is used, the corresponding function must be selected by ...
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PWC1 DW31 DW30 DW21 7 6 (BLOCK4) (BLOCK1) PWC0 AW1 AW0 IOW1 Data Wait (DW, IOW) DWn1/IOW1 DWn0/IOW0 READY signal is ignored. 2. Additional control by means ...
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REFRESH FUNCTION The following functions are provided to refresh DRAM and pseudo-SRAM. • Function to insert periodically a refresh cycle in a series of bus cycles • Refresh address output function to refresh DRAM and pseudo-SRAM • Function to ...
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INTERRUPT FUNCTIONS The V55PI incorporates a powerful interrupt controller (INTC) which controls multiple-interrupt servicing for a total of 25 maskable hardware interrupt requests: 19 internal and 6 external. The interrupt controller controls multiple-interrupt servicing based on programmable priority. The ...
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Interrupt Interrupt Default Request Interrupt Request Classification Priority Signal Control Register 1 NMI Nonmaskable –– 2 WDT 3 INTP0 IC9 4 INTP1 IC10 5 INTP2 IC11 6 INTP3 IC12 7 INTP4 IC13 8 INTP5 IC14 9 INTCM00 IC16 10 INTCM01 ...
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Interrupt Interrupt Default Request Classification Priority Interrupt Request Signal Control Register 19 INTSER0 IC26 20 INTSER1 IC27 INTSR0/ 21 IC28 INTCSI0 INTSR1/ 22 IC29 Maskable INTCSI1 23 INTST0 IC30 24 INTST1 IC31 25 INTSIT IC32 26 INTPAI IC36 27 INTAD ...
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INTERRUPT RESPONSE METHODS The V55PI has three interrupt response methods: a vectored interrupt function, register bank switching function, and macro service function. In the case of a maskable interrupt request, one of these functions can be selected by means ...
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Register Bank Switching Function In the V55PI, general register sets are mapped onto on-chip RAM, and register sets can be held banks. Interrupt servicing is performed by automatically switching the register bank when a BRKCS ...
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Macro Service Function The macro service function performs processing of simple data transfers, etc., by means of a microprogram (CPU internal dedicated firmware) started by generation of an interrupt request. The simple, standardized interrupt servicing which was coded and ...
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DMA FUNCTION (DMA CONTROLLER) The V55PI incorporates a 2-channel DMA controller which controls execution of memory-to-I/O or memory-to-memory DMA transfers on the basis of DMA requests generated by an on-chip peripheral hardware (serial interface, parallel interface, or timer), the ...
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DMA Start Source Transfer Mode On–Chip Software Peripheral Trigger Single transfer Available Available mode Demand release Not Available Not Available mode Single step Available* Available mode Burst Available* Available mode * The DMA start source is an on-chip timer interrupt, ...
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SERIAL INTERFACE FUNCTIONS The V55PI is equipped with a 2-channel serial interface unit (ch0, ch1). The two communication protocols supported by the V55PI are as follows: (1) Asynchronous UART (2) Clocked CSI 7.1 FEATURES Two communication protocols supported Two ...
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UART 7.3.1 Features Transfer rate 390 Kbps (with 12.5 MHz system clock ) 123 to 500 Kbps (with 16 MHz system clock ) Full-duplex operation capability On-chip dedicated (transmission and reception) baud rate generators Wake-up function Zero ...
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CLOCKED SERIAL INTERFACE (CSI) 7.4.1 Features Transfer speed: Max. 3.125 Mbps (with 12.5 MHz system clock ) Max. 4.0 Mbps (with 16 MHz system clock ) Half-duplex communication Data length: 8-bit unit External/internal clock selection function Data MSB-first/LSB-first selection ...
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PARALLEL INTERFACE FUNCTIONS The V55PI incorporates a parallel interface unit for data input on a Centronics specification interface, and general data input/output. 8.1 FEATURES The following features are provided as parallel interface functions: Centronics specification interface compatibility Input/output mode ...
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Figure 8-1. Parallel Interface Block Diagram (a) Input mode DATA RD RESET (b) Output mode DATA WR 54 Input Data Latch OE IBF S Q BUSY R Control Circuit MB0, 1 DMA ACK Request Control Circuit PAI Timer ACK Counter ...
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TIMER FUNCTION The V55PI timer unit can be used as an interval timer, free-running timer and event counter also possible to manipulate real-time output port, synchronized with interrupt requests generated by the timer. The ...
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Figure 9-1. Timer Unit Block Diagram Timer 0 /8 OVF 16–Bit Free Running Timer (TM0) Capture Register (CT00) INTP0 Capture Register (CT01) INTP1 INTCM00 Compare Register (CM00) INTCM01 Compare Register (CM01) Timer 2 Clear /8 16–Bit Timer Register 2 (TM2) ...
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REAL-TIME OUTPUT PORT FUNCTION Port 7 of the V55PI incorporates a real-time output port function, and can output the contents of the port 7 buffer (P7H, P7L) at programmable intervals from timer 0 bit-wise. 9.3.1 Real-Time Output Port Configuration ...
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Figure 9–2. Real–Time Output Port Operation TRG, BYTE Real–Time Output RTPC Port Control Register DLY 8 Internal Bus P7H P7L Port 7 Buffer Port 7 Buffer Output Latch RTP Bit 3 Output Latches RTP7 to RTP4 To Port 7 P77 ...
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Real-Time Output Port Operation Real-time output port specification is performed bit-wise by the port 7 mode control register (PCM7). Port 7 (P7), the port 7 buffer (P7H, P7L) and the real-time output port can be accessed as real-time output ...
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In particular possible to insert a delay time in the timing for output by setting the real-time output port delay specification register (RTPD) pins. If the P7L bit is changed from "1" to "0" possible to ...
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PWM UNIT The V55PI is provided with an 8-bit precision PWM (pulse width modulation) signal output function. PWM output can be used as a digital-to-analog conversion output by connecting a low-pass filter, etc., externally. This is ideal for the ...
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Figure 10-1. PWM Unit Block Diagram 8-Bit Counter Overflow Comparator Match Detection Signal PWM Slave Latch Preset PWM Register 0 0 Internal Bus PWM Active S Q Output Level R Q Control PWM Control ALV ...
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WATCHDOG TIMER FUNCTION The watchdog timer is a function for preventing inadvertent program looping and deadlocks. 11.1 FEATURES Three overflow times settable (8.1, 32.7, 131.0 [ms]: system clock clock = 12.5 MHz) Output pin provided (WDTOUT pin) which can ...
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A/D CONVERTER FUNCTION The V55PI incorporates a high-speed, high-precision 8-bit analog/digital (A/D) converter with four analog inputs (ANI0 to ANI3). The A/D converter uses the successive approximation method, and is provided with four A/D conversion result registers (ADCR0 to ...
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Figure 12-1. A/D Converter Block Diagram ANI0 Sample & Hold Circuit ANI1 ANI2 Input ANI3 Circuit P15/INTP4 External Trigger A/D Converter Mode Register (ADM) 8 Internal Bus Control Series Resistance String R/2 R R/2 Comparator Successive Approxi- 8 mation Register ...
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STANDBY FUNCTIONS The V55PI has two methods for controlling the operating clock as standby functions designed to reduce power dissipation. Transition to either of these standby modes is possible by means of a dedicated instruction. Table 13-1. HALT/STOP Mode ...
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STOP MODE In this mode, clock oscillation is stopped. This is effective when the entire application system is stopped, and offers extremely low power dissipation. The STOP mode is entered by executing the STOP instruction. In this mode all ...
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CLOCK GENERATOR The clock generator supplies various clocks to the CPU and peripheral hardware, and controls the CPU operating mode. 14.1 CLOCK GENERATOR CONFIGURATION AND OPERATION The clock generator is configured as shown in Figure 14-1. The clock generator ...
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In the V55PI, the frequency divider (time base counter: TBC) which divides the internal system clock is shared by each timer unit. The TBC cannot be read or written instruction. n The TBC tap output (divide-by-2 clock) ...
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SOFTWARE INTERVAL TIMER FUNCTION The V55PI incorporates a 16-bit software interval timer as a timer for software timer functions and watch functions. 15.1 SOFTWARE INTERVAL TIMER CONFIGURATION The configuration of the software interval timer is shown in Figure 15-1. ...
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CODEC INSTRUCTIONS The V55PI has 9 codec instructions. Using these special instructions on the V55PI enables not only image information MH encoding but also MR encoding which previously required the use of a special device such as an ACEE ...
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Figure 16-1. MH/MR Encoding Processing Flow No 72 Start Number of lines Yes Data transmission Data transmission instruction (EOL + tag instruction (EOL + tag bit "1" transmission) bit "0" transmission) ...
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Figure 16-2. MH and MR Decoding Processing Flow Start EOL detection instruction Error detection 1–bit detection instruction (tag bit detection) Tag = 1 MH decoding instruction Yes EOL detection at start No End Error detection No Pixel data creation instruction ...
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MEMORY MAP The data memory areas required by the V55PI's codec instructions are shown below. (1) Register file space This is the register bank for parameter setting. (2) User RAM Encoding line change point table : Storage area for ...
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Figure 16-3. Encoding Instructions and Data in Memory Register File Parameter Frame User ROM Encoding Conversion Table (512 Bytes case of MH/MR encoding instructions Figure 16-4. Decoding Instruction and Data in Memory Register File Parameter Frame User ...
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PROCESSING FLOW The instructions shown in 16.1 "Features" are used in the order shown in Figures 16-5 and 16-6 in encoding/decoding procesing. Figure 16-5. Processing Flow for Encoding of One Line Start Data transmission instruction (ALBIT) Transmission of EOL ...
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Figure 16-6. Processing Flow for Decoding of One Line Start EOL detection instruction (SCHEOL) EOL (000000000001) is detected 1 bit detection instruction (GETBIT) Tag (1 bit) is detected Input MH/MR decoding instruction (MHDEC/MRDEC) MH/MR decoding change point information for 1 ...
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INSTRUCTION SET The V55PI instruction set is upward compatible with the V20/V30 (native mode) and V25/V35 instruction sets. 17.1 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35 Instructions which have been added to the V20/V30 and V25/V35 instruction sets, and ...
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Instructions added to V25/V35. Mnemonic Operand IRAM None DS2 None DS3 None DS2, reg16, mem32 DS3, reg16, mem32 xsreg, reg16 MOV xsreg, mem16 reg16, xsreg mem16, xsreg DS2 PUSH DS3/VPC DS2 POP DS3/VPC RSTWDT imm8, imm8’ BTCLRL sfrl, imm3, ...
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INSTRUCTION SET OPERATIONS Identifier reg, 8/16-bit general register (Destination register in an instruction using two 8/16-bit general registers) reg’ Source register in an instruction using two 8/16-bit general registers reg8, 8-bit general register (Destination register in an instruction using ...
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Table 17-2. Operation Code Legend Identifier W Word/byte specification bit (1: word, 0: byte). However, when sign extension byte data is specified as 16-bit operand even reg, reg’ 8/16-bit general register specification bits ...
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Table 17-3. Operation Description Legend Identifier AW Accumulator (16 bits) AH Accumulator (high byte) AL Accumulator (low byte) BW Register BW (16 bits) CW Register CW (16 bits) CL Register CL (low byte) DW Register DW SP Stack pointer (16 ...
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Identifier (Blank) mod mem 000 001 010 011 100 IX 101 IY 110 Direct address 111 BW Note When BP is used in memory addressing other than in ...
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Number of Clock Cycles In the case of a memory operand the number of clock cycles depends on the addressing mode. The following numbers should be used for “EA” in Table 17-9 “Number of Clock Cycles”. mod 00 mem 000 ...
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Table 17-9. Number of Clock Cycles (1/20) Mnemonic Operands reg, reg' –– mem, reg –– 8 reg, mem 16 mem, imm –– reg, imm –– 8 acc, dmem 16 dmem, acc –– sreg, reg16 –– 8 xsreg, reg16 VPC, reg16 ...
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Table 17-9. Number of Clock Cycles (2/20) Mnemonic Operands AH, PSW –– MOV 8 PSW LDEA reg16, mem16 –– TRANS/ src-table –– TRANSB reg, reg' –– mem, reg/ XCH reg, mem AW, reg16/ –– reg16, AW MOVSPA –– ...
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Table 17-9. Number of Clock Cycles (3/20) Mnemonic Operands CMPM dst-block 8 CMPMB/ CMPMW 16 LDM src-block 8 LDMB/ LDMW 16 STM dst-block 8 STMB/ STMW 16 8 reg8, reg8' 16 INS 8 reg8, imm4 16 8 reg8, reg8' 16 ...
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Table 17-9. Number of Clock Cycles (4/20) Mnemonic Operands 8 acc8, imm8 16 IN*2 8 acc imm8, acc 16 OUT*2 8 DW, acc 16 8 dst-block, DW INM OUTM*2 DW, src-block ...
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Table 17-9. Number of Clock Cycles (5/20) Mnemonic Operands 8 acc8, imm8 acc imm8, acc 16 OUT 8 DW, acc 16 8 INM dst-block OUTM DW, src-block ...
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Table 17-9. Number of Clock Cycles (6/20) Mnemonic Operands reg, reg' –– 8 mem, reg 16 8 reg, mem ADD 16 reg, imm –– 8 mem, imm 16 acc, imm –– reg, reg' –– 8 mem, reg 16 8 reg, ...
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Table 17-9. Number of Clock Cycles (7/20) Mnemonic Operands reg, reg' –– 8 mem, reg 16 8 reg, mem 16 SUBC reg, imm –– 8 mem, imm 16 acc, imm –– 8 dst-string, ADD4S src-string 16 8 dst-string, SUB4S src-string ...
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Table 17-9. Number of Clock Cycles (8/20) Mnemonic Operands reg8 –– 8 mem8 16 MULU reg16 –– 8 mem16 16 reg8 –– 8 mem8 16 reg16 –– 8 mem16 16 reg16, reg16', MUL imm8/reg16, –– imm8 reg16, 8 mem16, imm8 ...
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Table 17-9. Number of Clock Cycles (9/20) Mnemonic Operands 8 reg8 16/63 + 10T mem8 16 DIVU 8 reg16 16/63 + 10T mem16 16 8 reg8 18/65 + ...
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Table 17-9. Number of Clock Cycles (10/20) Mnemonic Operands reg, reg' –– 8 mem, reg 16 8 reg, mem CMP 16 reg, imm –– 8 mem, imm 16 acc, imm –– reg –– 8 NOT mem 16 reg –– 8 ...
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Table 17-9. Number of Clock Cycles (11/20) Mnemonic Operands reg, reg' –– 8 mem, reg 16 8 reg, mem OR 16 reg, imm –– 8 mem, imm 16 acc, imm –– reg, reg' –– 8 mem, reg 16 8 reg, ...
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Table 17-9. Number of Clock Cycles (12/20) Mnemonic Operands reg8, CL –– 8 mem8 reg16, CL –– 8 mem16 NOT1 reg8, imm3 –– 8 mem8, imm3 16 reg16, imm4 –– 8 mem16, imm4 16 CY –– ...
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Table 17-9. Number of Clock Cycles (13/20) Mnemonic Operands reg8, CL –– 8 mem8 reg16, CL –– 8 mem16 reg8, imm3 –– SET1 8 mem8, imm3 16 reg16, imm4 –– 8 mem16, imm4 16 CY –– ...
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Table 17-9. Number of Clock Cycles (14/20) Mnemonic Operands reg, 1 –– 8 mem reg, CL –– SHR 8 mem reg, imm8 –– 8 mem, imm8 16 reg, 1 –– 8 mem reg, CL ...
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Table 17-9. Number of Clock Cycles (15/20) Mnemonic Operands reg, 1 –– 8 mem reg, CL –– ROR 8 mem reg, imm8 –– 8 mem, imm8 16 reg, 1 –– 8 mem reg, CL ...
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Table 17-9. Number of Clock Cycles (16/20) Mnemonic Operands 8 near-proc 16 8 regptr16 16 8 CALL memptr16 16 8 far-proc 16 8 memptr32 pop-value 16 RET pop-value mem16 16 ...
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Table 17-9. Number of Clock Cycles (17/20) Mnemonic Operands 8 mem16 16 8 reg16 16 8 sreg 16 POP 8 xsreg/VPC 16 8 PSW PREPARE*2 imm16, imm8 –– 8 DISPOSE 16 near-label –– short-label –– regptr16 ...
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Table 17-9. Number of Clock Cycles (18/20) Mnemonic Operands BV short-label –– BNV short-label –– BC/BL short-label –– BNC/BNL short-label –– BE/BZ short-label –– BNE/BNZ short-label –– BNH short-label –– BH short-label –– BN short-label –– BP short-label –– BPE ...
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Table 17-9. Number of Clock Cycles (19/20) Mnemonic Operands BRK*2 8 imm8 ( BRKV RETI 16 RETRBI –– FINT — 8 CHKIND*3 16 BRKCS reg16 –– *4 TSKSW reg16 –– HALT –– ...
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Table 17-9. Number of Clock Cycles (20/20) Mnemonic Operands 8 fp-op 16 FPO1 8 fp-op, mem 16 8 fp-op 16 FPO2 8 fp-op, mem 16 NOP –– RSTWDT imm8, imm8 –– QHOUT imm16 –– QOUT imm16 ...
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Operation Code Mnemonic Operand( reg, reg mem, reg reg, mem ...
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Operation Code Mnemonic Operand( AH, PSW MOV PSW LDEA reg16, mem16 ...
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Operation Code Mnemonic Operand( MOVBK dst-block, MOVBKB src-block MOVBKW CMPBK src-block, CMPBKB dst-block CMPBKW CMPM CMPMB ...
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Operation Code Mnemonic Operand( reg8, reg8 reg' reg INS reg8, imm4 ...
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Operation Code Mnemonic Operand( reg, reg mem, reg reg, mem ...
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Operation Code Mnemonic Operand( (dst-string, ADD4S src-string) (dst-string, SUB4S src-string) (dst-string, CMP4S ...
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Operation Code Mnemonic Operand( reg8 mem8 MULU reg16 ...
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Operation Code Mnemonic Operand( reg8 mem8 DIVU reg16 ...
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Operation Code Mnemonic Operand( reg8 mem8 DIV reg16 ...
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Operation Code Mnemonic Operand( ADJBA ADJ4A ADJBS ADJ4S ...
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Operation Code Mnemonic Operand( reg, reg mem, reg reg, mem TEST reg, imm ...
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Operation Code Mnemonic Operand( reg8 mem8 reg16 mem16 ...
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Operation Code Mnemonic Operand( reg8 mem8 reg16 mem16 ...
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Operation Code Mnemonic Operand( reg8 reg mem8 mod ...
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Operation Code Mnemonic Operand( reg mem reg ...
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Operation Code Mnemonic Operand( reg mem reg ...
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Operation Code Mnemonic Operand( reg mem reg ...
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Operation Code Mnemonic Operand( reg, imm8 ROLC mem, imm8 reg ...
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Operation Code Mnemonic Operand( near-proc regptr16 CALL memptr16 ...
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Operation Code Mnemonic Operand( DS3/VPC * PUSH mem16 reg16 reg sreg ...
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Operation Code Mnemonic Operand( short-label BNV short-label short-label BNC short-label ...
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Operation Code Mnemonic Operand( BRK imm8 BRKV ...
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Operation Code Mnemonic Operand( SCHEOL GETBIT MHDEC MRDEC ...
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ELECTRICAL SPECIFICATIONS This section shows the electrical specifications of the V55PI PD70433GD/R/GJ-12: PD70433-12 PD70433GD/R/GJ-16: PD70433-16 ABSOLUTE MAXIMUM RATINGS (T A PARAMETER Supply voltage Input voltage Output voltage Output current low Output current high Operating ambient temperature Storage temperature Notes ...
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DC Characteristics (T = – PARAMETER Input voltage low Input voltage high Schmitt-triggered input threshold voltage Schmitt-triggered input hysteresis width Output voltage low Output voltage high Input leakage current Output leakage current V supply current*4 ...
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RECOMMENDED OSCILLATION CIRCUIT The circuit shown below is recommended for a clock input. (1) Ceramic resonator connection ( OSCILLATOR MANUFACTURER FREQUENCY f [MHz] XX Murata Mfg. Co., Ltd Notes 1. The oscillator should be ...
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OSCILLATOR MANUFACTURER FREQUENCY f [MHz] XX Kinseki 25 32 Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other ...
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AC CHARACTERISTICS (T = – (1) PD70433-12 PARAMETER X1 input cycle time X1 input high-level width X1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle time CLKOUT output high-level ...
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PARAMETER ASTB delay time from RD , IORD RD , IORD delay time from WRL , WRH , IOWR DEX delay time from CLKOUT DEX hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold ...
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PARAMETER HLDAK delay time from HLDRQ Bus output delay time from HLDRQ HLDRQ low-level width HLDAK low-level width BUSLOCK delay time from CLKOUT DMARQm setup time (to CLKOUT ) DMARQm high-level width DMARQm low-level width DMARQm setup time (to CLKOUT ...
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PARAMETER CTS high-level width CTS low-level width Transmit/receive data cycle T C output clock cycle output clock high-level width output clock low-level width delay time from ...
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PD70433-16 PARAMETER X1 input cycle time X1 input high-level width X1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle time CLKOUT output high-level width CLKOUT output low-level width CLKOUT output rise time CLKOUT ...
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PARAMETER ASTB delay time from RD , IORD RD , IORD delay time from WRL , WRH , IOWR DEX delay time from CLKOUT DEX hold time (from CLKOUT ) Data input setup time (to CLKOUT ) Data input hold ...
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PARAMETER HLDAK delay time from HLDRQ Bus output delay time from HLDRQ HLDRQ low-level width HLDAK low-level width BUSLOCK delay time from CLKOUT DMARQm setup time (to CLKOUT ) DMARQm high-level width DMARQm low-level width DMARQm setup time (to CLKOUT ...
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PARAMETER CTS high-level width CTS low-level width Transmit/receive data cycle T C output clock cycle output clock high-level width output clock low-level width delay time from ...
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A/D CONVERTER CHARACTERISTICS (T PARAMETER SYMBOL Resolution Total error *1 Quantization error Conversion time t CONV Sampling time t SAMP Analog input voltage V IAN Analog input impedance R AN Reference voltage AV REF AV current AI REF REF T: ...
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AC Test Input Waveform *1 2 Except *2 AC Test Input Waveform * 0 RESET, P10/NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RxD0/SB1/SI0, P32/TxC/SCK0, P33/CTS0, P35/R D1/SI1, P36/SCK1/CTS1 X AC Test ...
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Clock Input/Output Timing 118 CLKOUT 9 Output Waveform (Except CLKOUT) 2.2 V 0.8 V 142 0 2 PD70433 DD 2.2 V 0.8 V ...
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Read Timing CLKOUT 17 A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus) ASTB 122 RAS*1 41 RD, IORD WRL, WRH, IOWR DEX Only activated when memory block (set by the MBS ...
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Write Timing CLKOUT 17 A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus) ASTB 122 RAS*1 RD, IORD WRL, WRH, IOWR DEX Only activated when memory block (set by the MBC register) ...
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Refresh Timing CLKOUT 17 A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus) ASTB 122 RAS 27 RD, IORD WRL, WRH, IOWR DEX* 127 REFRQ * Only valid when the external bus width is 16 bits. Remark ...
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Ready Input Timing (1) 1 data wait inserted T1 CLKOUT READY (2) 2 data waits inserted T1 CLKOUT READY (3) n data waits inserted ( CLKOUT 46 READY Remark The READY input becomes valid when the corresponding field ...
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DMA Timing (External Memory External I/O) CLKOUT A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus) ASTB RAS *1 RD WRL, WRH, IORD IOWR DMAAK0, DMAAK1 TCE0, *2 TCE1 DEX * Only activated when a ...
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DMA Timing (External I/O External Memory) CLKOUT A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus) ASTB RAS *1 RD, IOWR WRL, WRH IORD DMAAK0, DMAAK1 TCE0, *2 TCE1 DEX * Only activated when a ...
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INRPm Input Timing ( CLKOUT 52 INTP0-INTP5 NMI Input Timing CLKOUT NMI POLL Input Timing CLKOUT POLL PD70433 54 51 149 ...
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DMARQm Input Timing ( (1) In demand release mode (I/O-to-memory transfer) (a) Address wait not inserted CLKOUT ASTB DMAAK0, DMAAK1 68 DMARQ0, DMARQ1 (b) Address wait inserted CLKOUT ASTB DMAAK0, DMAAK1 68 DMARQ0, DMARQ1 (2) In ...
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Timer Output Timing CLKOUT TI1 TO00, TO01, TO20 TO21, TO30 WDTOUT Output Timing WDTOUT BUSLOCK Output Timing CLKOUT BUSLOCK Data Retention Timing (STOP Mode 117 131 132 133 133 115 116 PD70433 151 ...
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Hold Request/Acknowledge Timing (1) In normal mode CLKOUT 56 HLDRQ Bus Control Signal* HLDAK * ASTB, RD, WRH, WRL, DEX, RAS, BUSLOCK, IORD, IOWR, AD0 to AD15, A16 to A23 (2) Release of hold mode for refresh cycle insertion CLKOUT ...
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RESET Input Timing (1) STOP mode release/power-on reset CLKOUT RESET (2) System reset CLKOUT RESET CTSm Input Timing ( CTS0, CTS1 PD70433 153 ...
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Serial Interface Timing (1) 3-wire serial I/O mode 79 SCK0, SCK1 SI0, SI1 SO0, SO1 (2) SBI mode Bus release signal transfer timing SCK0 84 87 SB0, SB1 Command signal transfer timing SCK0 84 SB0, SB1 154 ...
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UART mode Transmit timing Output Data T D1 Output Data Receive timing Input Data R D0 Transmission enale timing CTS0, CTS1 ...
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Parallel Interface Timing (1) Input mode CLKOUT 96 DATASTB 99 PD0–PD7 BUSY (2) Output mode DATASTB 105 PD0–PD7 ACK BUSY 156 97 100 102 103 Input Data 104 101 98 Output Data 106 107 108 109 PD70433 ...
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Port Input/Output Timing CLKOUT Input Port Output Port T2/TI T3 T1/TI 124 125 123 PD70433 157 ...
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CHARACTERISTIC CURVES (FOR REFERENCE ONLY) –3.0 –2.0 –1 6.0 4.0 2 158 – ° 0.2 0.4 Supply Voltage – High-Level Output Voltage ...
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PACKAGE DRAWINGS 120 PIN PLASTIC QFP ( 28 120 1 G NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition ...
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PIN PLASTIC QFP (FINE PITCH 120 1 G NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. 160 20 ...
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PIN CERAMIC PGA A Index mark NOTE Each lead centerline is located within mm ( 0.020 inch) of its true position (T.P.) at maximum material condition. (Bottom View ...
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RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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PD70433 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. V20, V30, V25, V35, V25+, V55PI are trademarks of NEC Corporation. No part of this document may be copied or ...