UPD98431S1-F6 Renesas Electronics Corporation., UPD98431S1-F6 Datasheet
UPD98431S1-F6
Related parts for UPD98431S1-F6
UPD98431S1-F6 Summary of contents
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Mbps Ethernet DESCRIPTION The µ PD98431 is a 10/100 Mbps Ethernet controller having eight Media Access Control (MAC) ports conforming to IEEE 802.3 and IEEE 802.3u. Each port can store 1 packet of receive data since each port has ...
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BLOCK DIAGRAM FIFO FIFO DATA DATA BUS Common bus Interface CPU BUS CPU bus Interface TEST port JTAG SYSTEM CONFIGURATION EXAMPLE of SWITCH/ROUTER Line Interface Module (LIM) Optical 10/100M Module Multi-PHY Line Interface Module (LIM) Optical 10/100/1000M Module Multi-PHY 2 ...
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PIN CONFIGURATION 352-pin plastic BGA (35 × 35) µ PD98431S1-F6 Index mark 147 148 150 146 235 236 234 315 316 314 230 140 310 40 220 130 300 30 297 215 296 295 125 214 213 ...
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PIN NAMES Pin No. Pin Name Pin No. 1 (A1) TXFD30/FD62 51 (AF26) 2 (B1) TXFD29/FD61 52 (AE26) 3 (C1) TXFD26/FD58 53 (AD26) 4 (D1) TXFD23/FD55 54 (AC26) 5 (E1) TXFD20/FD52 55 (AB26) 6 (F1) TXFD17/FD49 56 (AA26) 7 (G1) ...
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Pin No. Pin Name Pin No. 201 (L3) TXFD3/FD35 239 (Y24) 202 (M3) TXFD2/FD34 240 (W24) 203 (N3) RXFDQ0/FDQ0 241 (V24) 204 (P3) RXFDQ3/FDQ3 242 (U24) 205 (R3) RXFD25/FD25 243 (T24) 206 (T3) RXFD22/FD22 244 (R24) 207 (U3) RXFD19/FD19 245 ...
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PIN FUNCTIONS (1) Register interface Pin Name Pin No. I/O CS# 70 Input RW 165 Input A[10:0] 251, 71, 166, 252, Input 72, 167, 253, 168, 73, 254, 255 D[31:0] 49, 50, 235, 51, I/O, 52, 148, 147, 53, ...
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FIFO interface Pin Name Pin No. I/O RXFEN#/ 68 Input FEN# TXFEN#/ 163 Input FRW FCLK 112 Input RXFPT[2: Output, 3-state Function FIFO bus reception enable/FIFO bus enable. The function of this signal differs as follows ...
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Pin Name Pin No. I/O TXFPT[2:0] 160, 66, 161 Input TXFD[31:0], 193 102, Input, RXFD[31:0]/ 101, 3, 194, 103, Output, FD[63:0] 4, 195, 104, 5, I/O, 196, 105, 6, 197, 3-state 106, 7, 282, 198, 107, 8, 199, ...
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Pin Name Pin No. I/O TXFBA[7:0] 156, 61, 245, 157, Output, 62, 246, 159, 158 3-state RXFA 113 Output, 3-state PASS 249 Input SKIP 69 Input Function Transmit FIFO buffer available. When these signals are high, the transmit FIFO has ...
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MII (Media Independent Interface) Pin Name Pin No. I/O TXCLK[7:0] 230, 137, 222, 29, Input 190, 92, 179, 174 TXD0[3:0] 258, 173, 80, 259 Output TXD1[3:0] 263, 178, 85, 265 Output TXD2[3:0] 91, 184, 268, 344 Output TXD3[3:0] 96, ...
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Pin Name Pin No. I/O TXD6[3:0] 135 Output TXD7[3:0] 141, 229, 45, 142 Output TXEN[7:0] 44, 136, 130, 125, Output 272, 183, 264, 79 RXCLK[7:0] 145, 227, 224, Input 218, 99, 187, 181, 83, RXD0[3:0] 175, 82, ...
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Pin Name Pin No. I/O Input RXD4[3:0] 30, 217, 128, 31 Input RXD5[3:0] 35, 223, 133, 36 Input RXD6[3:0] 226, 306, 42, 139 Input RXD7[3:0] 231, 47, 144, 232 Input CRS[7:0] 140, 37, 32, 26, 95, 89, 177, 257 Input ...
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JTAG pins (These functions can be supported upon request.) Pin Name Pin No. I/O Input TMS 256 Input TDI 76 TDO 74 Output 3-state Input TCK 169 Input TRST# 75 (5) Test pins and power pins Pin Name Pin ...
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PD98431 MII output signal pin connection When connecting the PHY device to the MII output signals (TXD, TTEN, TXER, MDC, MDIO), connect a serial resistor of 18 Ω Ω to each MII output ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Supply voltage Clamp supply voltage Input/output voltage Maximum power consumption Operating temperature Storage temperature Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, ...
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Characteristics (T A Parameter Input leakage current Output leakage current Operating current Clock input voltage, low Clock input voltage, high Input voltage, low Input voltage, high Output voltage, low Output ...
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Register Bus Interface Timing Parameter Note HCLK clock width HCLK low-level width HCLK high-level width RESET# pulse width A[10:0] setup time A[10:0] hold time RW setup time RW hold time CS# setup time CS# hold time ACK# output delay time ...
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HCLK timing t HKL HCLK HCLK RESET# (2) Register bus interface write timing HCLK t SHKA A[10:0] t SHKRW RW t SHKCS CS# t DHKAC ACK# Hi-Z t SHKD D[31:0] Hi-Z (3) Register bus interface read timing HCLK t ...
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Ethernet Transmit Interface Timing Parameter TXDn[3:0] delay time Transmit signal assert delay time Transmit signal deassert delay time TXCLK clock width TXCLK high-level width TXCLK low-level width (a) 10 Mbps serial mode CYTK TKH TKL TXCLK t ...
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Ethernet Receive Interface Timing Parameter RXDn[3:0] setup time RXDn[3:0] hold time Receive signal setup time Receive signal hold time RXCLK clock width RXCLK high-level width RXCLK low-level width (a) 10 Mbps serial mode t CYRK RXCLK t SRDRK RXDn [0] ...
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MII Management Interface Timing Parameter MDC cycle MDIO delay time MDIO setup time MDIO hold time MDC (a) Output MDC t DMCMD MDIO (output) FIFO Bus Interface Write Timing Parameter Note FCLK clock width FCLK high-level width FCLK low-level width ...
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FIFO bus interface write timing (32-bit dual bus mode) FCLK t SFKTE TXFEN# t DFKBA TXFBA[N] Hi-Z TXFDQ[3] TXFDQ[2] TXFDQ[1] t SFKDQ TXFDQ[0] t SFKTP TXFPT[2:0] t SFKFD TXFD[31:0] Idle Remark TXFBA[N ...
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FIFO bus interface write timing (64-bit single bus mode) FCLK t SFKRE FEN# t SFKTE FRW t DFKBA TXFBA[N] Hi-Z FDQ[3] FDQ[2] FDQ[1] t SFKDQ FDQ[0] t SFKTP TXFPT[2:0] t SFKFD FD[63:0] Idle Remark TXFBA[N ...
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FIFO Bus Interface Read Timing Parameter RXFA output delay time RXFA float time RXFDQ[3:0]/FDQ[3:0] output delay time RXFDQ[3:0]/FDQ[3:0] float time RXFPT[2:0] output delay time RXFPT[2:0] float time RXFD[31:0]/FD[63:0] output delay time RXFD[31:0]/FD[63:0] float time PASS setup time PASS hold time ...
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FIFO bus interface read timing (32-bit dual bus mode) 2 FCLK RXFEN# RXFA Hi-Z RXFDQ[3] Hi-Z RXFDQ[2] Hi-Z RXFDQ[1] Hi-Z RXFDQ[0] Hi-Z RXFPT[2:0] Port number N Hi-Z RXFD[31:0] Hi-Z PASS SKIP Skip frame XX Port number N 1st 1st ...
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FIFO bus interface read timing (32-bit dual bus mode) 3 FCLK t SFKRE RXFEN# RXFA Hi-Z RXFDQ[3] Hi-Z RXFDQ[2] Hi-Z RXFDQ[1] Hi-Z RXFDQ[0] Hi-Z RXFPT[2:0] Hi-Z RXFD[31:0] Hi-Z PASS SKIP DFKFA DFKFA t DFKDQ t t ...
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FIFO bus interface read timing (32-bit dual bus mode) 4 FCLK RXFEN# RXFA RXFDQ[3] RXFDQ[2] RXFDQ[1] RXFDQ[0] RXFPT[2:0] RXFD[31:0] PASS SKIP t HFKRE t FFKFA Hi-Z t DFKDQ t FFKDQ Hi DFKDQ FFKDQ Hi DFKDQ ...
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FIFO bus interface read timing (64-bit single bus mode) 1 FCLK t SFKRE FEN# t SFKTE FRW t DFKFA RXFA Hi-Z t DFKDQ FDQ[3] Hi-Z t DFKDQ FDQ[2] Hi-Z t DFKDQ FDQ[1] Hi-Z t DFKDQ FDQ[0] Hi-Z t DFKRP ...
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FIFO bus interface read timing (64-bit single bus mode) 2 FCLK FEN# FRW RXFA Hi-Z FDQ[3] Hi-Z FDQ[2] Hi-Z FDQ[1] Hi-Z FDQ[0] Hi-Z RXFPT[2:0] Port number N Hi-Z FD[63:0] Hi-Z PASS SKIP Skip frame XX Port number N 1st ...
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FIFO bus interface read timing (64-bit single bus mode) 3 FCLK t SFKRE FEN# t SFKTE FRW RXFA Hi-Z FDQ[3] Hi-Z FDQ[2] Hi-Z FDQ[1] Hi-Z FDQ[0] Hi-Z RXFPT[2:0] Hi-Z FD[63:0] Hi-Z PASS SKIP DFKFA DFKFA t ...
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FIFO bus interface read timing (64-bit single bus mode) 4 FCLK FEN# FRW RXFA FDQ[3] FDQ[2] FDQ[1] FDQ[0] RXFPT[2:0] FD[63:0] PASS SKIP t HFKRE t HFKTE t FFKFA Hi-Z t DFKDQ t FFKDQ Hi DFKDQ DFKDQ ...
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Boundary Scan (JTAG) Timing Parameter TCK clock width TCK low-level width TCK high-level width TDI setup time TDI hold time TDO output delay time TMS setup time TMS hold time TCK TDI TDO TMS 32 Symbol Conditions t CYJK t ...
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PACKAGE DRAWING 352-PIN PLASTIC BGA (35x35 Index mark φ φ ...
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RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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The information in this document is current as of March, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date ...