HMP9701CN Intersil Corporation, HMP9701CN Datasheet
HMP9701CN
Related parts for HMP9701CN
HMP9701CN Summary of contents
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... Thus, reducing noise and lowering the cost of implementation. Ordering Information TEMP. o PART NUMBER RANGE ( C) Page HMP9701CN HMP9701EVAL2 PCI Bus Evaluation Board (Includes codec) † TQFP is also known as PQFP and MQFP. 1 AC’97 Audio Codec PACKAGE PKG. NO. ...
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Functional Block Diagram HMP9701 AC’97 AUDIO CODEC MIC1 GAIN 0dB/20dB MIC2 LINE_IN CD VIDEO AUX PHONE MONO MONO_OUT VOL MASTER LINE_OUT VOL GAM PC_BEEP STEREO SIGNAL PATH MONO SIGNAL PATH Functional Description The HMP9701 is a full-duplex ...
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Analog Mixer The Analog Mixer generates two outputs, one stereo and one mono. The stereo output is used to drive LINE_OUT and is composed of a stereo mix of all analog input sources and the audio output from the DACs. ...
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TAG PHASE SYNC 12.288MHz 81.4ns BIT_CLK SLOT SLOT SDATA_OUT 1 2 VALID FRAME TIME SLOT “VALID” BITS (“1” = TIME SLOT CONTAINS VALID DATA) “1” = FRAME CONTAINS VALID DATA The HMP9701 generates a serial bit clock (BIT_CLK) at 12.288MHz ...
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TABLE 1. BIT MAP FOR SLOT 1: CONTROL ADDRESS BITS DESCRIPTION COMMENT 19 Read/Write 1 = Read Write 18:12 Control Register Identifies the Target Control Register Index 11:0 Reserved Set to “0” Audio Output Slot 2: Control Data ...
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Input Audio Slot 2: Status Data This slot delivers control register read data. TABLE 6. BIT MAP FOR SLOT 1: STATUS DATA BITS DESCRIPTION 19:4 Control Register Stuffed with 0’s if slot tagged invalid Read Data 3:0 Reserved Stuffed with ...
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AC Link Powerdown The AC-link interface can be placed in a low power mode by setting PR4 = 1 in the Powerdown Register (see above). In this mode, both BIT_CLK and SDATA_IN are forced to a logic “low” voltage level. ...
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Testability The HMP9701 provides a test mode to support the in circuit test capabilities provided by automatic test equipment (ATE). In this mode, the HMP9701 drives its digital AC-Link outputs (BIT_CLK and SDATA_IN high impedance state. This allows ...
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TABLE 15. RECORD SELECT LEFT CHANNEL SL2:0 RIGHT RECORD SOURCE 0 MIC 1 CD_L 2 VIDEO_L 3 AUX_L 4 LINE_IN_L 5 Stereo Mix Right 6 Mono Mix 7 PHONE Default: 000 (MIC in) Record Gain Registers (Index 1Ch and 1Eh) ...
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REG NAME D15 D14 D13 00h Reset 02h Master Volume Mute X ML5 04h Reserved 06h Master Volume Mono Mute X X 08h Reserved 0Ah PC_BEEP Volume Mute X X 0Ch ...
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Pinout V DD XTL_IN XTL_OUT GND SDATA_OUT BIT_CLK GND SDATA_IN V DD SYNC RESET PC_BEEP Pin Descriptions TQFP PIN INPUT/ NAME NUMBER OUTPUT DIGITAL I/O RESET 11 I RESET - This active low signal causes a HMP9701 hardware reset that ...
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Pin Descriptions (Continued) TQFP PIN INPUT/ NAME NUMBER OUTPUT LINE_IN_R 24 I Right Line Input. The right line-level may be selected for recording via one of the stereo ADC’s via the Input Mux. In addition, this input can be gained/attenuated ...
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... Operating Conditions Temperature Range HMP9701CN CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... BCP t Note 3 BCH t Note 3 BCL Note CRL t R2BC t SRH t S2BC t PDWN t SU2RST t Note 3 HZ MIN TYP 0 - 0.4xFs - - - 0.6xFs - HMP9701CN MIN TYP MAX UNITS - 12.288 - MHz - 81 32.56 - 48.84 ns 32.56 - 48. kHz - 20 BCP - 240 * BCP ...
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Analog-to-Digital Converters (Notes 2, 4) PARAMETER Resolution Signal-to-Noise Line Inputs Mic Inputs (Mic Gain = 0dB) Total Harmonic Distortion Line Mic Interchannel Isolation Line/Line Line/Mic Line/Aux Line/Video Gain Error (Full Scale) Inter-Channel Gain Mismatch Offset Error (0dB Gain) Gain Drift ...
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Programmable Attenuation/Gain PARAMETER Master Volume Span for LINE_OUT, MONO_OUT (0dB to -46.5dB) Master Volume Step Size Mixer Input Gain Span for LINE_IN, CD, VIDEO, AUX, PHONE, MIC (+12dB to -34.5dB) Mixer Input Gain Step SIze PC_BEEP Attenuation Span (0dB to ...
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Typical Performance Curves 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 FREQUENCY (xF FIGURE 10. ANALOG-TO-DIGITAL FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB -10 -20 -30 -40 -50 -60 -70 -80 -90 ...
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AC Timing Waveforms t R2BC t CRL RESET BIT_CLK FIGURE 16. COLD RESET TIMING t S2BC t SRH SYNC BIT_CLK FIGURE 18. WARM RESET TIMING t t BCH BIT_CLK t SH SYNC FIGURE 20. CLOCKS BIT_CLK SDATA_IN SDATA_OUT SYNC HMP9701 ...
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Typical Application Schematic Diagram AC_LINK INTERFACE SD_OUT 1 BIT_CLK 2 SD_IN ‘97 COMPLIANT SYNC 4 CONTROLLER/INTERFACE IC RESET 5 6 1.0 F PC_BEEP 1.0 F PHONE 1.0 F AUX LEFT 1.0 F AUX RIGHT 1.0 F VIDEO ...
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Typical Application Schematic Notes 1. A note about the capacitors used for coupling externally input audio or for outputting audio externally: The capacitance value and the associated circuit imped- ances will determine the lower frequency cutoff of the au- dio ...