ADP3181 Analog Devices, ADP3181 Datasheet
ADP3181
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ADP3181 Summary of contents
Page 1
... The ADP3181 also includes programmable no-load offset and slope functions to adjust the output voltage as a function of the load current so that it is always optimally positioned for a system transient. The ADP3181 provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed power good output that accommodates on-the-fly output voltage changes requested by the CPU ...
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... ADP3181 TABLE OF CONTENTS Specifications..................................................................................... 3 Test Circuits....................................................................................... 5 Absolute Maximum Ratings............................................................ 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ........................................................................ 9 Start-Up Sequence........................................................................ 9 Master Clock Frequency............................................................ 10 Output Voltage Differential Sensing ........................................ 10 Output Current Sensing ............................................................ 10 Active Impedance Control Mode............................................. 10 Current Control Mode and Thermal Balance ........................ 10 Voltage Control Mode ...
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... T V RAMPADJ − FB. RAMPADJ I RAMPADJ V CSSUM − CSREF. See Figure 2. OS(CSA) I BIAS(CSSUM) GBW (CSA pF. CSCOMP CSSUM and CSREF. ΔV See Figure CSCOMP Rev Page ADP3181 Min Typ Max Unit 0.7 3.1 V −14.5 +14.5 mV 0.05 % μA 14 15.5 17 μA 100 140 μA 500 20 MHz 25 V/μ ...
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... ADP3181 Parameter CURRENT BALANCE CIRCUIT Common Mode Range Input Resistance Input Current Input Current Matching CURRENT LIMIT COMPARATOR Output Voltage Normal Mode In Shutdown Output Current, Normal Mode 2 Maximum Output Current Current Limit Threshold Voltage Current Limit Setting Ratio Delay Normal Mode Voltage ...
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... CSCOMP– 12V 28 + 1μF 100nF 20kΩ 100nF Rev Page ADP3181 ADP3181 VCC 12V 10kΩ COMP 9 200kΩ CSCOMP 18 100nF 200kΩ CSSUM 17 Δ V CSREF 16 1.0V GND 19 Δ Δ – FB Δ ...
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... ADP3181 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter VCC FBRTN VID0 to VID4, CPUID, EN, DELAY, ILIMIT, CSCOMP, RT, PWM1 to PWM4, COMP SW1 to SW4 All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (θ Lead Temperature Soldering (10 sec) Infrared (15 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device ...
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... Current Limit Set Point/Enable Output. An external resistor from this pin to GND sets the current limit threshold of the converter. This pin is actively pulled low when the ADP3181 EN input is low, or when V below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low ...
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... ADP3181 TYPICAL PERFORMANCE CHARACTERISTICS 100 150 R VALUE (kΩ) T Figure 6. Master Clock Frequency vs. R 200 250 300 T Rev Page 5 25°C A 4-PHASE OPERATION 5.2 5.1 5.0 4.9 4.8 4.7 4.6 0 0.5 1.0 1.5 2.0 2.5 3.0 OSCILLATOR FREQUENCY (MHz) Figure 7. Supply Current vs. Oscillator Frequency 3.5 4.0 ...
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... VID DAC operates with five inputs and generates the VR 9 output voltage range, as shown in Table 4. If CPUID is <4 V, the VID DAC treats CPUID as the VID5 input and operates as a 6-bit DAC using the output voltage range given in Table 5. Table VID Codes for ADP3181JRU Only, CPUID >4.25 VID4 VID3 VID2 1 ...
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... ADP3181 MASTER CLOCK FREQUENCY The clock frequency of the ADP3181 is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 6. To determine the frequency per phase, the clock is divided by the number of phases in use. If PWM4 is grounded, then divide the master clock by 3 for the frequency of the remaining phases ...
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... The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. Table VID Codes for the ADP3181, CPUID Used As a VID5 Input VID4 VID3 VID2 ...
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... PWRGD threshold, then a soft start cycle is initiated. The latch-off function can be reset by removing and reapplying V to the ADP3181 pulling the EN pin low for a short CC time. To disable the short circuit latch-off function, the external , with a secondary DLY resistor to ground should be left open and a high value (> ...
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... The VCC to the controller must be higher than the UVLO threshold and the EN pin must be higher then its logic threshold for the ADP3181 to begin switching. IF UVLO is less than the threshold or the EN pin is a logic low, the device is disabled. This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and holds the ILIMIT pin at ground ...
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... DRVH 1 8 IPD12N03L PGND 6 4 VCC DRVL 5 C15 4.7μF Q8 IPD06N03L IPD06N03L + C19 C20 1μF 33μ 383kΩ ADP3181 VCC 1 VID4 28 PWM1 2 VID3 27 VID2 PWM2 VID1 PWM3 25 5 VID0 PWM4 24 6 CPUID SW1 FBRTN SW2 8 SW3 ...
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... APPLICATIONS The design parameters for a typical ADP3181 CPU application are as follows: • Input voltage ( • VID setting voltage ( 1.500 V VID • Duty cycle (D) = 0.125 • Nominal output voltage at no load (V • Nominal output voltage load ( • Static output voltage drop based on a 1.5 mΩ load line (R from no load to full load: (VΔ ...
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... ADP3181 If the ripple voltage is less than that designed for, the inductor can be made smaller until the ripple value is met. This allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. A 300 nH inductor is a good choice to start, and it gives a calculated ripple current of 13 ...
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... Solving for R CS2 TH and 35.30 kΩ and 78.11 kΩ. Choosing the CS1 CS2 . The value of R can be found using − VID ONL − 480 Ω μA SELECTION ADP3181 (10) (11 (12) ...
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... The maximum output current requirement for the low-side (synchronous) MOSFETs. In the ADP3181, currents are balanced between phases, so the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (n dominant, the following expression shows the total power being dissipated in each synchronous MOSFET in terms of the ripple ...
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... VID V × × × − × 0 125 × × Ω 267 kHz ADP3181 ⎤ × ⎥ (19 ⎥ ⎦ × for the mA GMF (20) (21) ...
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... PCB and component parasitic effects. Using Equations 24 to 28, compute the time constants for all the poles and zeros in the system, where, for the ADP3181 the PCB resistance from the bulk capacitors to the ceramics and R is approximately the total low-side MOSFET on-resistance DS per phase at 25° ...
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... That inductor also acts as a filter between the converter and the primary power source. Rev Page and an amplitude of one-nth of the OUT × × × CRMS × × − 125 CRMS × 125 ADP3181 (33 ...
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... VID DAC and load line accordingly. This can be accomplished using the BOOTSELECT output from the CPU. Figure 12 shows how this signal is used to modify the load line and set the CPUID pin of the ADP3181 appropriately. 100nF BOOTSELECT Figure 12. Connections to Allow Automatic Switching between VR9 and VR10 Operation ...
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... If critical signal lines (including the output voltage sense lines of the ADP3181) must cross through power circuitry best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier ...
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... COPLANARITY 0.010 0.004 COPLANARITY ORDERING GUIDE Part Number Temperature Package 1 ADP3181JRUZ-REEL 0°C to +85° ADP3181JRQZ-RL 0°C to +85° PB-free part. 2 VRD10 only. ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 9.80 9.70 9.60 ...