NCP5201 ON Semiconductor, NCP5201 Datasheet

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NCP5201

Manufacturer Part Number
NCP5201
Description
Manufacturer
ON Semiconductor
Datasheet

Specifications of NCP5201

Dc
04+

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NCP5201MNR2G
Manufacturer:
ON
Quantity:
2 500
NCP5201
Dual Output
DDR Power Controller
designed as a total power solution for a high current DDR memory
system. This IC combines the efficiency of a PWM controller for the
VDDQ supply with the simplicity of a linear regulator for the VTT
memory termination voltage. The secondary regulator (VTT) is
designed to automatically track at half the primary regulator voltage
(VDDQ). An internal power good voltage monitor tracks both
VDDQ and VTT outputs and notifies the user in the event of a fault
on either output. Protective features include soft−start circuitry and
undervoltage monitoring of VCC and VSTBY. The IC is packaged in
a 5 × 6 QFN−18.
Features
Typical Applications
*For additional information on our Pb−Free strategy and soldering details, please
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 11
download the ON Semiconductor Soldering and Mounting Techniques Reference
Manual, SOLDERRM/D.
The NCP5201 Dual DDR Power Controller is specifically
Incorporates VDDQ, VTT Regulators
Internal Switching Standby Regulator for VDDQ
All External Power MOSFETs Are N−Channel
Adjustable VDDQ
VTT Tracks VDDQ/2
Fixed Switching Frequency of 250 kHz for VDDQ in Normal Mode
Doubled Switching Frequency (500 kHz) for Standby Mode
Soft−Start Protection for VDDQ
Undervoltage Monitor
Short−Circuit Protection for Both VDDQ and VTT Outputs
Housed in a space saving 5 × 6 QFN−18
Pb−Free Packages are Available*
DDR Termination Voltage
Active Termination Busses (SSTL−2, SSTL−3)
1
NCP5201MN
NCP5201MNG
NCP5201MNR2
NCP5201MNR2G
NOTE:
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
OCDDQ
FBDDQ
VSTBY
FBVTT
18−LEAD QFN, 5 x 6 mm
PGND
VDDQ
Device
(Note: Microdot may be in either location)
VTT
VTT
NC
Pin 19 is the thermal pad on the bottom of
the device.
MN SUFFIX
ORDERING INFORMATION
CASE 505
1
A
WL = Wafer Lot
YY
WW = Work Week
G
PIN CONNECTIONS
http://onsemi.com
1
2
3
4
5
6
7
8
9
= Assembly Location
= Year
= Pb−Free Package
18−Lead QFN
18−Lead QFN
18−Lead QFN 2500/T ape & Reel
18−Lead QFN
(Pb−Free)
(Pb−Free)
Package
Publication Order Number:
1
18
17
16
15
14
13
12
11
10
AWLYYWW G
2500/T ape & Reel
MARKING
DIAGRAM
NCP5201
61 Units / Rail
61 Units / Rail
Shipping
NCP5201/D
G
SS
COMP
VCC
TGDDQ
BGDDQ
SDDQ
AGND
S3_EN
PWRGD

Related parts for NCP5201

NCP5201 Summary of contents

Page 1

... NCP5201 Dual Output DDR Power Controller The NCP5201 Dual DDR Power Controller is specifically designed as a total power solution for a high current DDR memory system. This IC combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of a linear regulator for the VTT memory termination voltage ...

Page 2

... Human Body Model (HBM) ≤ 2.0 kV per JEDEC Standard JESD22−A114 except Pin 15 which is ≤ 1.5 kV. Machine Model (MM) ≤ 200 V per JEDEC Standard JESD22−A115 except Pin 14 which is ≤ 100 V. 2. Latchup Current Maximum Rating: ≤ 150 mA per JEDEC Standard JESD78. NCP5201 L1 1 ...

Page 3

... Unity Gain Bandwidth Slew Rate VTT ACTIVE TERMINATOR VTT Tracking VDDQ Mode Source Current Limit Sink Current Limit 3. Guaranteed by design, not tested in production. NCP5201 = 0 to 70° 1.7 mH, COUT = 3770 mF, COUT2 = 220 mF, A Symbol Test Conditions IST_S0 S3_EN = LOW, VCC = 12 V IST_S3 ...

Page 4

... TH_PAD Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ NCP5201 = 0 to 70° 1.7 mH, COUT = 3770 mF, COUT2 = 220 mF, (VSTBY = 5.0 V, VCC = Symbol Test Conditions − ...

Page 5

... VST− VSTBY UVLO + VSTGD − VREF PWRGD S0 OSC PGND S3 SS SC2PWR + R − SC2GND + R − GND AGND NCP5201 VREF VREFGD TSD S0 Control S3 12 VGD Logic INREGDDQ INREGVTT ILIM VDDQ PWM Logic S0 S3 PWM− COMP + − AMP S3 S0 INREGDDQ INREGVTT ...

Page 6

... DETAILED OPERATION DESCRIPTIONS General The NCP5201 Dual DDR Power Controller combines the efficiency of a PWM controller for the VDDQ supply with the simplicity of a linear regulator for the VTT memory termination voltage. VTT is designed to automatically track at half VDDQ. The inclusion of an internal PWM switching FET for VDDQ standby operation, both VDDQ and VTT power good voltage monitors, soft− ...

Page 7

... S0 when VDDQ is in regulation standby mode in state S3. When in normal mode and VTT is in regulation, signal INREGVTT NCP5201 operate in discontinuous conduction mode (DCM) in the S3 state. And, switching in doubled frequency (500 kHz reduce the peak conduction current. In this operating mode, the body diode of the external synchronous MOSFET acts as a flywheel diode and the MOSFET is never turned on ...

Page 8

... S5 VSTGD goes HIGH INREGVTT goes HIGH INREGDDQ goes HIGH, VTT is activated 12 VGD goes HIGH, VDDQ is activated Figure 3. Power−Up and Power−Down Timing Diagram NCP5201 VTT in H− S3_EN goes HIGH, INREGVTT VTT goes into standby goes HIGH mode, then INREGVTT ...

Page 9

... COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.18 0.30 D 6.00 BSC D2 3.98 4.28 E 5.00 BSC E2 2.98 3.28 e 0.50 BSC K 0.20 −−− L 0.45 0.65 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NCP5201/D ...

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