XC68HC711E9CFS2 Freescale Semiconductor, Inc, XC68HC711E9CFS2 Datasheet
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M68HC11E Family Data Sheet HC11 Microcontrollers M68HC11E Rev. 5.1 07/2005 freescale.com ...
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...
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... The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. ...
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Revision History Revision Date Level 2.3.3.1 System Configuration Register — Addition to NOCOP bit description May, 2001 3.1 Added 10.21 EPROM Characteristics 10.21 EPROM Characteristics — For clarity, addition to note 2 following the June, 2001 3.2 table December, 7.7.2 ...
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List of Chapters Chapter 1 General Description ...
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List of Chapters 6 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Table of Contents 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.4.3 EPROM and EEPROM Programming Control Register 2.5 EEPROM ...
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Data Types ...
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Table of Contents 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 10.15 Expansion Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Chapter 1 General Description 1.1 Introduction This document contains a detailed description of the M68HC11 E series of 8-bit microcontroller units (MCUs). These MCUs all combine the M68HC11 central processor unit (CPU) with high-performance, on-chip peripherals. The E series is ...
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General Description • Computer operating properly (COP) watchdog system • 38 general-purpose input/output (I/O) pins: – 16 bidirectional I/O pins – 11 input-only pins – 11 output-only pins • Several packaging options: – 52-pin plastic-leaded chip carrier (PLCC) – 52-pin ...
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MODA/ MODB/ LIR V XTAL EXTAL E STBY OSC MODE CONTROL CLOCK LOGIC TIMER SYSTEM BUS EXPANSION ADDRESS PORT A PORT applies only to devices with EPROM/OTPROM. PPE Figure 1-1. M68HC11 E-Series Block Diagram Freescale Semiconductor IRQ ...
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General Description XTAL PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 RESET * XIRQ/V PD0/RxD * V applies only to devices with EPROM/OTPROM. PPE Figure 1-2. Pin Assignments for 52-Pin PLCC and CLCC ...
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PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5 1. V applies only to devices with EPROM/OTPROM. PPE Figure 1-3. Pin Assignments for 64-Pin QFP Freescale Semiconductor ...
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General Description PA0/IC3 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PE0/AN0 PE4/AN4 PE1/AN1 PE5/AN5 1. V applies only to devices with EPROM/OTPROM. PPE Figure 1-4. Pin Assignments for 52-Pin TQFP ...
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PC0/ADDR0/DATA0 PC1/ADDR1/DATA1 PC2/ADDR2/DATA2 PC3/ADDR3/DATA3 PC4/ADDR4/DATA4 PC5/ADDR5/DATA5 PC6/ADDR6/DATA6 PC7/ADDR7/DATA7 * V Figure 1-5. Pin Assignments for 56-Pin SDIP Freescale Semiconductor MODB/V STBY 2 MODA/LIR 3 STRA/ STRB/R/W 6 EXTAL 7 XTAL ...
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General Description PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OC1 PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 MODB/V Figure 1-6. Pin Assignments for 48-Pin DIP (MC68HC811E2 PA2/IC1 43 6 PA1/IC2 42 7 PA0/IC3 ...
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V and Power is supplied to the MCU through V operates from a single 5-volt (nominal) power supply. Low-voltage devices in the E series operate at 3.0–5.5 volts. Very fast signal transitions occur on the MCU ...
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General Description 1.4.2 RESET A bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either ...
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EXTAL MCU XTAL Figure 1-9. Common Parallel Resonant Crystal Connections MCU Figure 1-10. External Oscillator Connections 1.4.4 E-Clock Output ( the output connection for the internally generated E clock. The signal from E is used as a timing ...
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General Description IRQ must be configured for level-sensitive operation if there is more than one source of IRQ interrupt. There should be a single pullup resistor near the MCU interrupt input pin (typically 4.7 kΩ). There must also be an ...
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STRA/AS The strobe A (STRA) and address strobe (AS) pin performs either of two separate functions, depending on the operating mode: • In single-chip mode, STRA performs an input handshake (strobe input) function. • In the expanded multiplexed mode, ...
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General Description Port/Bit PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 — — PE0 PE1 PE2 PE3 PE4 ...
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PA6–PA4 serve as either general-purpose outputs, timer input captures, or timer output compare 2–4. In addition, PA6–PA4 can be controlled by OC1. PA3 can be a general-purpose I/O pin or a timer IC/OC pin. Timer functions associated with this pin ...
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General Description 1.4.15 Port D Pins PD5–PD0 can be used for general-purpose I/O signals. These pins alternately serve as the serial communication interface (SCI) and serial peripheral interface (SPI) signals when those subsystems are enabled. • PD0 is the receive ...
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Chapter 2 Operating Modes and On-Chip Memory 2.1 Introduction This section contains information about the operating modes and the on-chip memory for M68HC11 E-series MCUs. Except for a few minor differences, operation is identical for all devices in the E ...
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Operating Modes and On-Chip Memory The address, R/W, and AS signals are active and valid for all bus cycles, including accesses to internal memory locations. The E clock is used to enable external devices to drive data onto the internal ...
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ROM at $BFC0–$BFFF. The bootstrap ROM contains a small program which initializes the serial communications interface (SCI) and allows the user to download a program into on-chip RAM. The size of the downloaded program can be as ...
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Operating Modes and On-Chip Memory $0000 EXT $1000 EXT $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 2-3. Memory Map for MC68HC11E1 $0000 EXT $1000 EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP Figure 2-4. Memory Map for MC68HC(7)11E9 32 0000 ...
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EXT $1000 EXT $9000 EXT $B600 EXT $D000 $FFFF SINGLE EXPANDED CHIP * 20 Kbytes ROM/EPROM are contained in two segments of 8 Kbytes and 12 Kbytes each. Figure 2-5. Memory Map for MC68HC(7)11E20 $0000 EXT $1000 EXT $F800 ...
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Operating Modes and On-Chip Memory Addr. Register Name Port A Data Register $1000 (PORTA) See page 98. $1001 Reserved Parallel I/O Control Register $1002 (PIOC) See page 102. Port C Data Register $1003 (PORTC) See page 99. Port B Data ...
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Addr. Register Name Output Compare 1 Data Register $100D (OC1D) See page 136. Timer Counter Register High $100E (TCNTH) See page 137. Timer Counter Register Low $100F (TCNTL) See page 137. Timer Input Capture 1 Register $1010 High (TIC1H) See ...
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Operating Modes and On-Chip Memory Addr. Register Name Timer Output Compare 2 Register $1019 Low (TOC2L) See page 134. Timer Output Compare 3 Register $101A High (TOC3H) See page 135. Timer Output Compare 3 Register $101B Low (TOC3L) See page ...
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Addr. Register Name Timer Interrupt Flag 2 $1025 (TFLG2) See page 142. Pulse Accumulator Control Regis- $1026 ter (PACTL) See page 142. Pulse Accumulator Count Regis- $1027 ter (PACNT) See page 146. Serial Peripheral Control Register $1028 (SPCR) See page ...
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Operating Modes and On-Chip Memory Addr. Register Name Analog-to-Digital Results $1031 Register 1 (ADR1) See page 64. Analog-to-Digital Results $1032 Register 2 (ADR2) See page 64. Analog-to-Digital Results $1033 Register 3 (ADR3) See page 64. Analog-to-Digital Results $1034 Register 4 ...
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Addr. Register Name $103E Reserved System Configuration Register $103F (CONFIG) See page 43. System Configuration Register (3) $103F (CONFIG) See page 43. 1. Can be written only once in first 64 cycles out of reset in normal modes or at ...
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Operating Modes and On-Chip Memory 4.8-V NiCd Figure 2-8. RAM Standby MODB/V The bootloader program is contained in the internal bootstrap ROM. This ROM, which appears as internal memory space at locations $BF00–$BFFF, is enabled only if the MCU is ...
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Table 2-1. Hardware Mode Select Summary Input Levels at Reset MODB MODA normal mode is selected when MODB is logic 1 during reset. One of three reset vectors is fetched from address $FFFA–$FFFF, and program ...
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Operating Modes and On-Chip Memory 0 0 IRV(NE) — Internal Read Visibility (Not E) Bit IRVNE can be written once in any mode. In expanded modes, IRVNE determines whether IRV off. In special test mode, IRVNE is ...
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System Configuration Register The system configuration register (CONFIG) consists of an EEPROM byte and static latches that control the startup configuration of the MCU. The contents of the EEPROM byte are transferred into static working latches during reset sequences. ...
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Operating Modes and On-Chip Memory Address: $103F Bit 7 Read: EE3 Write: Resets: Single chip: 1 Bootstrap: 1 Expanded: U Test indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in ...
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NOSEC — Security Disable Bit NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If the security mask option is omitted NOSEC always reads 1. The enhanced security feature is available in the MC68S711E9 ...
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Operating Modes and On-Chip Memory Table 2-4. RAM Mapping RAM[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 2.3.3.3 System Configuration Options Register The 8-bit, special-purpose system configuration options register (OPTION) sets ...
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IRQE — Configure IRQ for Edge-Sensitive Only Operation Bit Refer to Chapter 5 Resets and DLY — Enable Oscillator Startup Delay Bit 0 = The oscillator startup delay coming out of stop mode is bypassed and the MCU resumes processing ...
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Operating Modes and On-Chip Memory 2.4.1 Programming an Individual EPROM Address • In this method, the MCU programs its own EPROM by controlling the PPROG register (EPROG in MC68HC711E20). Use these procedures to program the EPROM through the MCU with: ...
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EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register (PPROG) enables the EPROM programming voltage and controls the latching of data to be programmed. • For MC68HC711E9, PPROG is also the EEPROM programming control register. ...
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Operating Modes and On-Chip Memory Address: $1036 Bit 7 Read: MBE Write: Reset: 0 Figure 2-15. MC68HC711E20 EPROM Programming MBE — Multiple-Byte Programming Enable Bit When multiple-byte programming is enabled, address bit 5 is considered a don’t care so that ...
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PGM — EPROM Programming Voltage Enable Bit PGM can be read any time and can be written only when ELAT = Programming voltage to EPROM array disconnected 1 = Programming voltage to EPROM array connected 2.5 EEPROM ...
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Operating Modes and On-Chip Memory Address: $1035 Bit 7 Read: Write: Reset: 0 Figure 2-16. Block Protect Register (BPROT) Bits [7:5] — Unimplemented Always read 0 PTCON — Protect CONFIG Register Bit 0 = CONFIG register can be programmed or ...
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EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register (PPROG) selects and controls the EEPROM programming function. Bits in PPROG enable the programming voltage, control the latching of data to be programmed, and select the ...
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Operating Modes and On-Chip Memory EPGM — EPROM/OTPROM/EEPROM Programming Voltage Enable Bit 0 = Programming voltage to EEPROM array switched off 1 = Programming voltage to EEPROM array switched on During EEPROM programming, the ROW and BYTE bits of PPROG ...
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EEPROM Byte Erase This is an example of how to erase a single byte of EEPROM. BYTEE LDAB #$16 STAB $103B STAB 0,X LDAB #$17 STAB $103B JSR DLY10 CLR $103B 2.5.1.6 CONFIG Register Programming Because the CONFIG register ...
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Operating Modes and On-Chip Memory 56 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Chapter 3 Analog-to-Digital (A/D) Converter 3.1 Introduction The analog-to-digital (A/D) system, a successive approximation converter, uses an all-capacitive charge redistribution technique to convert analog signals to digital values. 3.2 Overview The A/D system is an 8-channel, 8-bit, multiplexed-input converter. The ...
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Analog-to-Digital (A/D) Converter PE0 AN0 PE1 AN1 PE2 AN2 PE3 AN3 ANALOG MUX PE4 AN4 PE5 AN5 PE6 AN6 PE7 AN7 ADR1 A/D RESULT 1 Figure 3-1. A/D Converter Block Diagram ANALOG INPUT PIN < INPUT PROTECTION DEVICE ...
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Digital Control All A/D converter operations are controlled by bits in register ADCTL. In addition to selecting the analog input to be converted, ADCTL bits indicate conversion status and control whether single or continuous conversions are performed. Finally, the ...
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Analog-to-Digital (A/D) Converter 3.3 A/D Converter Power-Up and Clock Select Bit 7 of the OPTION register controls A/D converter power-up. Clearing ADPU removes power from and disables the A/D converter system. Setting ADPU enables the A/D converter system. Stabilization of ...
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Conversion Process The A/D conversion sequence begins one E-clock cycle after a write to the A/D control/status register, ADCTL. The bits in ADCTL select the channel and the mode of conversion. An input voltage equal to V converts to ...
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Analog-to-Digital (A/D) Converter 3.7 Multiple-Channel Operation The two types of multiple-channel operation are: 1. When SCAN = 0, a selected group of four channels is converted one time each. The first result is stored in A/D result register 1 (ADR1), ...
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When this control bit is clear, the four requested conversions are performed once to fill the four result registers. When this control bit is set, conversions are performed continuously with the result registers updated as data becomes available. MULT — ...
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Analog-to-Digital (A/D) Converter 3.10 A/D Converter Result Registers These read-only registers hold an 8-bit conversion result. Writes to these registers have no effect. Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register ...
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Chapter 4 Central Processor Unit (CPU) 4.1 Introduction Features of the M68HC11 Family include: • Central processor unit (CPU) architecture • Data types • Addressing modes • Instruction set • Special operations such as subroutine calls and interrupts The CPU ...
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Central Processor Unit (CPU) 4.2.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single ...
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At the end of the interrupt service routine, an return-from interrupt (RTI) instruction is executed. The RTI instruction causes the saved registers to be pulled off the stack in reverse order. Program execution resumes at the return address. Certain instructions ...
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Central Processor Unit (CPU) 4.2.5 Program Counter (PC) The program counter, a 16-bit register, contains the address of the next instruction to be executed. After reset, the program counter is initialized from one of six possible vectors, depending on operating ...
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Interrupt Mask (I) The interrupt request (IRQ) mask (I bit global mask that disables all maskable interrupt sources. While the I bit is set, interrupts can become pending, but the operation of the CPU continues uninterrupted until ...
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Central Processor Unit (CPU) 4.4 Opcodes and Operands The M68HC11 Family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range ...
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Extended In the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. These are 3-byte instructions (or 4-byte instructions if a prebyte is required). One or two bytes are needed ...
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Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description ⇒ A ABA Add Accumulators ⇒ IX ABX Add ( ...
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Table 4-2. Instruction Set (Sheet Mnemonic Operation Description ? ⊕ BGT (rel) Branch if > Zero BHI (rel) Branch Higher BHS (rel) Branch if ...
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Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description CMPB (opr) Compare – M Memory $FF – M ⇒ M COM (opr) Ones Complement Memory Byte $FF – A ⇒ A ...
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Table 4-2. Instruction Set (Sheet Mnemonic Operation Description ⇒ B INCB Increment Accumulator ⇒ SP INS Increment Stack Pointer ⇒ IX INX Increment Index Register X IY ...
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Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description LSRD Logical Shift Right Double ∗ B ⇒ D MUL Multiply – M ⇒ M ...
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Table 4-2. Instruction Set (Sheet Mnemonic Operation Description A – M – C ⇒ A SBCA (opr) Subtract with Carry from A B – M – C ⇒ B SBCB (opr) Subtract with Carry from B 1 ...
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Central Processor Unit (CPU) Table 4-2. Instruction Set (Sheet Mnemonic Operation Description TSTA Test A for Zero A – Minus TSTB Test B for Zero B – Minus ⇒ IX ...
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Chapter 5 Resets and Interrupts 5.1 Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current instruction ...
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Resets and Interrupts 5.2.2 External Reset (RESET) The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic 1 in less than two E-clock cycles after an internal device releases reset. When ...
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Address $103A Bit 7 Read: BIT 7 Write: Reset: 0 Figure 5-1. Arm/Reset COP Timer Circuitry Register (COPRST) Complete this 2-step reset sequence to service the COP timer: 1. Write $55 to COPRST to arm the COP timer clearing mechanism. ...
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Resets and Interrupts 5.2.5 System Configuration Options Register Address: $1039 Bit 7 Read: ADPU Write: Reset Can be written only once in first 64 cycles out of reset in normal mode or at any time in special modes ...
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Configuration Control Register Address: $103F Bit 7 Read: EE3 Write: Reset: 0 Figure 5-3. Configuration Control Register (CONFIG) EE[3:0] — EEPROM Mapping Bits EE[3:0] apply only to MC68HC811E2. Refer to NOSEC — Security Mode Disable Bit Refer to Chapter ...
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Resets and Interrupts 5.3.2 Memory Map After reset, the INIT register is initialized to $01, mapping the RAM at $00 and the control registers at $1000. For the MC68HC811E2, the CONFIG register resets to $FF. EEPROM mapping bits (EE[3:0]) place ...
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Analog-to-Digital (A/D) Converter The analog-to-digital (A/D) converter configuration is indeterminate after reset. The ADPU bit is cleared by reset, which disables the A/D system. The conversion complete flag is indeterminate. 5.3.10 System The EEPROM programming controls are disabled, so ...
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Resets and Interrupts Any one of these interrupts can be assigned the highest maskable interrupt priority by writing the appropriate value to the PSEL bits in the HPRIO register. Otherwise, the priority arrangement remains the same. An interrupt that is ...
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Table 5-3. Highest Priority Interrupt Selection PSEL[3: ...
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Resets and Interrupts Table 5-4. Interrupt and Reset Vector Assignments Vector Address FFC0, C1 – FFD4, D5 Reserved FFD6, D7 FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB ...
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Refer to Chapter 4 Central Processor Unit Table 5-5. Stacking ...
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Resets and Interrupts 5.5.4 Software Interrupt (SWI) SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhibited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit, once ...
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HIGHEST PRIORITY POWER-ON RESET (POR) DELAY 4064 E CYCLES LOAD PROGRAM COUNTER WITH CONTENTS OF $FFFE, $FFFF (VECTOR FETCH) Figure 5-5. Processing Flow Out of Reset (Sheet Freescale Semiconductor EXTERNAL RESET CLOCK MONITOR FAIL (WITH CME = ...
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Resets and Interrupts STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF8, $FFF9 STACK CPU REGISTERS SET BIT I IN CCR FETCH VECTOR $FFF6, $FFF7 Figure 5-5. Processing Flow Out of Reset (Sheet ...
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BEGIN X BIT IN CCR SET ? NO HIGHEST PRIORITY INTERRUPT ? NO IRQ ? NO RTII = IC1I = IC2I = IC3I = OC1I = 1 ? ...
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Resets and Interrupts 2A Y OC2I = OC3I = OC4I = I4/O5I = TOI = PAOVI = PAII = ...
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BEGIN Y FLAG RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 5-7. Interrupt Source Resolution Within SCI 5.6.2 Stop ...
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Resets and Interrupts masked), the MCU starts up, beginning with the stacking sequence leading to normal service of the XIRQ request set to 1 (XIRQ masked or inhibited), then processing continues with the instruction that immediately follows ...
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Chapter 6 Parallel Input/Output (I/O) Ports 6.1 Introduction All M68HC11 E-series MCUs have five input/output (I/O) ports and I/O lines, depending on the operating mode. Refer to Table 6-1 Input Port Pins Port A 3 Port B ...
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Parallel Input/Output (I/O) Ports 6.2 Port A Port A shares functions with the timer system and has: • Three input-only pins • Three output-only pins • Two bidirectional I/O pins Address: $1000 Bit 7 Read: PA7 Write: Reset: I Alternate ...
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Port B In single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded or special test modes, port B pins are high-order address outputs. Address: $1004 Bit 7 Single-chip or bootstrap modes: Read: PB7 Write: Reset: 0 ...
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Parallel Input/Output (I/O) Ports PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin, port C data is latched into the PORTCL register. Reads of this register return the last value latched into ...
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Port E Port E is used for general-purpose static inputs or pins that share functions with the analog-to-digital (A/D) converter system. When some port E pins are being used for general-purpose input and others are being used as A/D ...
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Parallel Input/Output (I/O) Ports 6.8 Parallel I/O Control Register The parallel handshake functions are available only in the single-chip operating mode. PIOC is a read/write register except for bit 7, which is read only. operations. STAF Clearing HNDS Sequence Read ...
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CWOM — Port C Wired-OR Mode Bit (affects all eight port C pins customary to have an external pullup resistor on lines that are driven by open-drain devices Port C outputs are normal CMOS outputs. 1 ...
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Parallel Input/Output (I/O) Ports 104 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Chapter 7 Serial Communications Interface (SCI) 7.1 Introduction The serial communications interface (SCI universal asynchronous receiver transmitter (UART), one of two independent serial input/output (I/O) subsystems in the M68HC11 E series of microcontrollers. It has a standard non-return-to-zero ...
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Serial Communications Interface (SCI) TRANSMITTER BAUD RATE CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Note: Refer to Figure ...
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Receive Operation During receive operations, the transmit sequence is reversed. The serial shift register receives data and transfers parallel receive data register (SCDR complete word. This double buffered operation allows a character to be ...
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Serial Communications Interface (SCI) RECEIVER BAUD RATE CLOCK DDD0 SEE NOTE PIN BUFFER PD0 AND CONTROL RxD DISABLE DRIVER SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Note: Refer to Figure B-1. EVBU Schematic Diagram 108 ÷16 DATA ...
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Address-Mark Wakeup The serial characters in this type of wakeup consist of seven (eight information bits and an MSB, which indicates an address character (when set mark). The first character of each ...
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Serial Communications Interface (SCI) 7.7.1 Serial Communications Data Register SCDR is a parallel register that performs two functions: • The receive data register when it is read • The transmit data register when it is written Reads access the receive ...
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Serial Communications Control Register 2 The SCCR2 register provides the control bits that enable or disable individual SCI functions. Address: $102D Bit 7 Read: TIE Write: Reset: 0 Figure 7-5. Serial Communications Control Register 2 (SCCR2) TIE — Transmit ...
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Serial Communications Interface (SCI) 7.7.4 Serial Communication Status Register The SCSR provides inputs to the interrupt logic circuits for generation of the SCI system interrupt. Address: $102E Bit 7 Read: TDRE Write: Reset Unimplemented Figure 7-6. Serial Communications ...
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FE — Framing Error Flag FE is set when detected where a stop bit was expected. Clear the FE flag by reading SCSR with FE set and then reading SCDR Stop bit detected 1 = ...
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Serial Communications Interface (SCI) Prescaler Selects SCP2 SCP1 SCP0 SCR2 SCR1 SCR0 ...
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SCR[2:0] — SCI Baud Rate Select Bits Selects receiver and transmitter bit rate based on output from baud rate prescaler stage. Refer to Figure 7-8 and Figure 7-9. The prescaler bits, SCP[2:0], determine the highest baud rate, and the SCR[2:0] ...
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Serial Communications Interface (SCI) EXTAL OSCILLATOR CLOCK GENERATOR XTAL *SCP2 is present only on MC68HC(7)11E20. Figure 7-9. MC68HC(7)11E20 SCI Baud Rate 7.8 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by ...
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TDRE and TC flags are normally set when the transmitter is first enabled (TE set to 1). The TDRE flag indicates there is room in the transmit queue to store another data character in the TDR. The TIE bit is ...
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Serial Communications Interface (SCI) BEGIN FLAG Y RDRF = TDRE = IDLE = VALID SCI REQUEST Figure 7-10. Interrupt Source Resolution ...
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Chapter 8 Serial Peripheral Interface (SPI) 8.1 Introduction The serial peripheral interface (SPI), an independent serial communications subsystem, allows the MCU to communicate synchronously with peripheral devices, such as: • Frequency synthesizers • Liquid crystal display (LCD) drivers • Analog-to-digital ...
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Serial Peripheral Interface (SPI) INTERNAL MCU CLOCK DIVIDER ÷2 ÷4 ÷16 ÷32 SELECT SPI CONTROL SPI STATUS REGISTER SPI INTERRUPT REQUEST 8.4 Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity ...
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SCK CYCLE # SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT MSB (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE ASSERTED 2. MASTER WRITES TO SPDR ...
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Serial Peripheral Interface (SPI) 8.5.3 Serial Clock SCK, an input to a slave device, is generated by the master device and synchronizes data movement in and out of the device through the MOSI and MISO lines. Master and slave devices ...
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A write collision is normally a slave error because a slave has no control over when a master initiates a transfer. A master knows when a transfer is in progress, so there is no reason for a master to generate ...
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Serial Peripheral Interface (SPI) MSTR — Master Mode Select Bit It is customary to have an external pullup resistor on lines that are driven by open-drain devices Slave mode 1 = Master mode CPOL — Clock Polarity Bit ...
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Bit 5 — Unimplemented Always reads 0 MODF — Mode Fault Bit To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to Select and 8.6 SPI System Errors mode ...
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Serial Peripheral Interface (SPI) 126 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Chapter 9 Timing Systems 9.1 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer’s programmable prescaler provides ...
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Timing Systems OSCILLATOR AND CLOCK GENERATOR (DIVIDE BY FOUR) PRESCALER (÷ 16, 32) SPR[1:0] PRESCALER (÷ 13) SCP[1: ÷ ÷ PRESCALER (÷ 16) PR[1:0] TCNT IC/OC ...
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Control Bits PR1, PR0 count — overflow — count — overflow — count — overflow — count — overflow — 9.2 Timer Structure Figure 9-2 shows the capture/compare ...
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Timing Systems PRESCALER DIVIDE BY TCNT (HI MCU PR1 PR0 E CLK 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 ...
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The control and status bits that implement the input capture functions are contained in: • Pulse accumulator control register (PACTL) • Timer control 2 register (TCTL2) • Timer interrupt mask 1 register (TMSK1) • Timer interrupt flag 2 register (TFLG1) ...
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Timing Systems input capture register pair inhibits a new capture transfer for one bus cycle double-byte read instruction, such as load double accumulator D (LDD), is used to read the captured value, coherency is assured. When a new ...
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Timer Input Capture 4/Output Compare 5 Register Use TI4/O5 as either an input capture register or an output compare register, depending on the function chosen for the PA3 pin. To enable input capture pin, set the ...
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Timing Systems OC1 is different from the other output compares in that a successful OC1 compare can affect any or all five of the OC pins. The OC1 output action taken when a match is found is controlled by two ...
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Register name: Timer Output Compare 3 Register (High) Bit 7 Read: Bit 15 Write: Reset: 1 Register name: Timer Output Compare 3 Register (Low) Bit 7 Read: Bit 7 Write: Reset: 1 Figure 9-10. Timer Output Compare 3 Register Pair ...
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Timing Systems FOC[1:5] — Force Output Comparison Bit When the FOC bit associated with an output compare circuit is set, the output compare circuit immediately performs the action it is programmed to do when an output match occurs ...
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Timer Counter Register The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read addresses the most significant byte (MSB) first. A read of this address causes the least significant byte (LSB) to ...
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Timing Systems 9.4.7 Timer Interrupt Mask 1 Register Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts. Address: $1022 Bit 7 Read: OC1I Write: Reset: 0 Figure 9-17. Timer Interrupt Mask 1 Register ...
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Timer Interrupt Mask 2 Register Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The timer prescaler control bits are included in this register. Address: $1024 Bit 7 Read: TOI Write: Reset Unimplemented ...
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Timing Systems 9.4.10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have occurred. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either ...
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For this reason, an RTI period starts from the previous timeout, not from when RTIF is cleared. Every timeout causes the RTIF bit in TFLG2 to be set, and ...
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Timing Systems 9.5.2 Timer Interrupt Flag Register 2 Bits of this register indicate the occurrence of timer system events. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a ...
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PEDGE — Pulse Accumulator Edge Control Bit Refer to 9.7 Pulse Accumulator. DDRA3 — Data Direction for Port A Bit 3 Refer to Chapter 6 Parallel Input/Output (I/O) I4/O5 — Input Capture 4/Output Compare Bit Refer to 9.7 Pulse Accumulator. ...
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Timing Systems ÷ CLOCK FROM MAIN TIMER MCU PIN PA7/ INPUT BUFFER PAI/ AND OC1 EDGE DETECTOR OUTPUT BUFFER FROM MAIN TIMER OC1 FROM DDRA7 144 TMSK2 INT ENABLES PAI EDGE PAEN CLOCK : 2 1 MUX DATA ...
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Pulse Accumulator Control Register Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5 function or the IC4 function, while two other bits select the rate for the real-time interrupt system. Address: ...
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Timing Systems 9.7.2 Pulse Accumulator Count Register This 8-bit read/write register contains the count of external input events at the PAI input or the accumulated count. The PACNT is readable even if PAI is not active in gated time accumulation ...
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PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable Bit and Flag The PAIF status bit is automatically set each time a selected edge is detected at the PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 ...
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Timing Systems 148 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Chapter 10 Electrical Characteristics 10.1 Introduction This section contains electrical specifications for the M68HC11 E-series devices. 10.2 Maximum Ratings for Standard and Extended Voltage Devices Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed ...
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Electrical Characteristics 10.3 Functional Operating Range Rating Operating temperature range MC68HC(7)11Ex MC68HC(7)11ExC MC68HC(7)11ExV MC68HC(7)11ExM MC68HC811E2 MC68HC811E2C MC68HC811E2V MC68HC811E2M MC68L11Ex Operating voltage range 10.4 Thermal Characteristics Characteristic Average junction temperature Ambient temperature Package thermal resistance (junction-to-ambient) 48-pin plastic DIP (MC68HC811E2 only) ...
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DC Electrical Characteristics Characteristics (2) Output voltage = ±±10.0 µA I Load All outputs except XTAL All outputs except XTAL, RESET, and MODA (2) Output high voltage I = –0.8 mA 4.5 V Load DD All outputs ...
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Electrical Characteristics 10.6 Supply Currents and Power Dissipation Characteristics (2) Run maximum total supply current Single-chip mode2 MHz 3 MHz Expanded multiplexed mode2 MHz 3 MHz (2) Wait maximum total supply current (all peripheral functions shut down) Single-chip mode2 MHz ...
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MC68L11E9/E20 DC Electrical Characteristics Characteristics (2) Output voltage = ±±10.0 µA I Load All outputs except XTAL All outputs except XTAL, RESET, and MODA (2) Output high voltage I = –0.5 mA 3.0 V Load DD I ...
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Electrical Characteristics 10.8 MC68L11E9/E20 Supply Currents and Power Dissipation Characteristic (2) Run maximum total supply current Single-chip mode Expanded multiplexed mode 5.5 V ...
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CLOCKS, STROBES INPUTS ~ V DD OUTPUTS ~ TESTING ~ V DD CLOCKS, STROBES INPUTS OUTPUTS TESTING Notes: 1. Full test loads are applied during all dc ...
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Electrical Characteristics 10.9 Control Timing (1) (2) Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time PCSU CYC Reset input pulse width To guarantee external reset vector ...
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MC68L11E9/E20 Control Timing Characteristic Frequency of operation E-clock period Crystal frequency External oscillator frequency Processor control setup time PCSU CYC Reset input pulse width To guarantee external reset vector Minimum input time ...
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V DD EXTAL 4064 t CYC E RESET MODA, MODB FFFE FFFE FFFE ADDRESS Figure 10-3. POR External Reset Timing Diagram t PCSU PW RSTL t MPS NEW FFFE FFFF FFFE FFFE FFFE PC t MPH NEW FFFE FFFE FFFF ...
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INTERNAL CLOCKS 1 IRQ PW IRQ IRQ or XIRQ t STOPDELAY E STOP STOP 4 ADDRESS ADDR ADDR + 1 STOP STOP 5 ADDRESS ADDR ADDR + 1 Notes : 1. Edge Sensitive IRQ pin (IRQE bit = 1) 2. ...
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E IRQ, XIRQ, OR INTERNAL INTERRUPTS WAIT WAIT ADDRESS SP SP – 1 ADDR ADDR + 1 PCL PCH, YL, YH, XL, XH CCR STACK REGISTERS R/W Note: RESET also causes recovery from WAIT. Figure 10-5. WAIT Recovery ...
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E t PCSU 1 IRQ PW IRQ 2 IRQ , XIRQ, OR INTERNAL INTERRUPT NEXT NEXT ADDRESS SP SP – 1 OPCODE DATA – – PCL CODE R/W Notes : 1. Edge sensitive IRQ pin (IRQE ...
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Electrical Characteristics 10.11 Peripheral Port Timing (1) (2) Characteristic Frequency of operation E-clock frequency E-clock period Peripheral data setup time MCU read of ports and E Peripheral data hold time MCU read of ports ...
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MC68L11E9/E20 Peripheral Port Timing Characteristic Frequency of operation E-clock frequency E-clock period Peripheral data setup time MCU read of ports and E Peripheral data hold time MCU read of ports and E Delay ...
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Electrical Characteristics Figure 10-9. Simple Input Strobe Timing Diagram E E PORT B PREVIOUS PORT DATA PORT B PREVIOUS PORT DATA STRB (OUT) STRB (OUT) Figure 10-10. Simple Output Strobe Timing Diagram E E STRB (OUT) STRB (0UT) STRA (IN) ...
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WRITE PORTCL WRITE PORTCL E E PORT C (OUT) PREVIOUS PORT DATA PORT C (OUT) PREVIOUS PORT DATA STRB (IN) STRB (OUT) STRA (IN) STRA (IN) Notes: NOTES: 1. After reading PIOC with STAF set 1. After reading PIOC with ...
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Electrical Characteristics 10.13 Analog-to-Digital Converter Characteristics (1) Characteristic Resolution Number of bits resolved by A/D converter Maximum deviation from the ideal A/D transfer Non-linearity characteristics Difference between the output of an ideal and an Zero error actual for 0 input ...
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MC68L11E9/E20 Analog-to-Digital Converter Characteristics (1) Characteristic Resolution Number of bits resolved by A/D converter Maximum deviation from the ideal A/D transfer Non-linearity characteristics Difference between the output of an ideal and an Zero error actual for 0 input voltage ...
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Electrical Characteristics 10.15 Expansion Bus Timing Characteristics Num Characteristic Frequency of operation (E-clock frequency) 1 Cycle time (2) 2 Pulse width, E low , (2) 3 Pulse width, E high , ...
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MC68L11E9/E20 Expansion Bus Timing Characteristics Num Characteristic Frequency of operation (E-clock frequency) 1 Cycle time Pulse width, E low 1 Pulse width, E high 1 and AS ...
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Electrical Characteristics E E R/W, ADDRESS R/W, ADDRESS NON-MULTIPLEXED (NON-MUX READ READ ADDRESS/DATA ADDRESS/DATA MULTIPLEXED (MULTIPLEXED) WRITE WRITE Note: Measurement points shown are 20% and 70 NOTE: Measurement points shown ...
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Serial Peripheral Interface Timing Characteristics (1) Num Characteristic Frequency of operation E clock E-clock period Operating frequency Master Slave Cycle time 1 Master Slave (2) Enable lead time 2 Slave (2) Enable lag time 3 Slave Clock (SCK) high ...
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Electrical Characteristics 10.18 MC68L11E9/E20 Serial Peirpheral Interface Characteristics (1) Num Characteristic Frequency of operation E clock E-clock period Operating frequency Master Slave Cycle time 1 Master Slave (2) Enable lead time 2 Slave (2) Enable lag time 3 Slave Clock ...
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SS INPUT SCK CPOL = 0 SEE NOTE INPUT SCK CPOL = 1 SEE NOTE OUTPUT MISO INPUT MOSI OUTPUT Note: This first clock edge is generated internally but is not seen at the SCK pin. SS INPUT SCK CPOL ...
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Electrical Characteristics SS INPUT SCK CPOL = 0 INPUT 2 SCK CPOL = 1 INPUT 8 MISO SLAVE OUTPUT 6 MOSI MSB IN INPUT Note: Not defined but normally MSB of character just received SS INPUT SCK CPOL = 0 ...
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EEPROM Characteristics (1) Characteristic (2) Programming time < 1.0 MHz, RCO enabled 1.0 to 2.0 MHz, RCO disabled ≥ 2.0 MHz (or anytime RCO enabled) (2) Erase time Byte, row, and bulk Write/erase endurance Data retention = 5.0 Vdc ...
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Electrical Characteristics 176 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Chapter 11 Ordering Information and Mechanical Specifications 11.1 Introduction This section provides ordering information for the E-series devices grouped by: • Standard devices • Custom ROM devices • Extended voltage devices In addition, mechanical specifications for the following packaging options: ...
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Ordering Information and Mechanical Specifications Description 52-pin plastic leaded chip carrier (PLCC) (Continued) OTPROM OTPROM, enhanced security feature 20 Kbytes OTPROM No ROM, 2 Kbytes EEPROM 64-pin quad flat pack (QFP) BUFFALO ROM No ROM No ROM, no EEPROM 20 ...
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Description 52-pin windowed ceramic leaded chip carrier (CLCC) EPROM 20 Kbytes EPROM 48-pin dual in-line package (DIP) — MC68HC811E2 only No ROM, 2 Kbytes EEPROM 56-pin dual in-line package with 0.70-inch lead spacing (SDIP) BUFFALO ROM No ROM No ROM, ...
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Ordering Information and Mechanical Specifications Description 20 Kbytes custom ROM 64-pin quad flat pack (QFP) Custom ROM 64-pin quad flat pack (continued) 20 Kbytes Custom ROM 52-pin thin quad flat pack ( mm) Custom ROM 56-pin dual ...
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Extended Voltage Device Ordering Information (3.0 Vdc to 5.5 Vdc) Description 52-pin plastic leaded chip carrier (PLCC) Custom ROM No ROM No ROM, no EEPROM 64-pin quad flat pack (QFP) Custom ROM No ROM No ROM, no EEPROM 52-pin ...
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Ordering Information and Mechanical Specifications 11.5 52-Pin Plastic-Leaded Chip Carrier (Case 778) –N– –L– 0.010 (0.25) T L– VIEW S 182 B Y BRK D Z –M– W ...
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Windowed Ceramic-Leaded Chip Carrier (Case 778B) -A- R 0.51 (0.020 Freescale Semiconductor 52-Pin Windowed Ceramic-Leaded Chip Carrier (Case 778B) 0.51 (0.020 - ...
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Ordering Information and Mechanical Specifications 11.7 64-Pin Quad Flat Pack (Case 840C –D– A 0.20 (0.008 0.05 (0.002) A–B S 0.20 (0.008 DETAIL ...
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Thin Quad Flat Pack (Case 848D) 4X 0.20 (0.008) H L– –L– –H– –T– SEATING PLANE 0.05 (0.002 Freescale Semiconductor 4X TIPS N 0.20 (0.008) T L–M ...
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Ordering Information and Mechanical Specifications 11.9 56-Pin Dual in-Line Package (Case 859) –A– –T– SEATING PLANE 0.25 (0.010 11.10 48-Pin Plastic DIP (Case 767) The MC68HC811E2 is the only member ...
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Appendix A Development Support A.1 Introduction This section provides information on the development support offered for the E-series devices. A.2 M68HC11 E-Series Development Tools Device Package MC68HC11E9 MC68HC711E9 MC68HC11E20 MC68HC711E20 ...
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Development Support A.4 Modular Development System (MMDS11) The M68MMDS11 modular development system (MMDS11 emulator system for developing embedded systems based on an M68HC11 microcontroller unit (MCU). The MMDS11 provides a bus state analyzer (BSA) and real-time memory windows. ...
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Extensive on-line MCU information via the CHIPINFO command. View memory map, vectors, register, and pinout information pertaining to the device being emulated • Host software supports: – An editor – An assembler and user interface – Source-level debug – ...
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Development Support 190 M68HC11E Family Data Sheet, Rev. 5.1 Freescale Semiconductor ...
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Appendix B EVBU Schematic Refer to Figure B-1 for a schematic diagram of the M68HC11EVBU Universal Evaluation Board. This diagram is included for reference only. Freescale Semiconductor M68HC11E Family Data Sheet, Rev. 5.1 191 ...
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MCU 0.1 µF 1 µF MCU 33 33 MCU 32 32 MCU 31 31 MCU 30 30 MCU 29 29 MCU 28 28 MCU MCU 20 20 MCU 21 ...
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... Driving bootstrap mode from another M68HC11 • Driving bootstrap mode from a personal computer • Common bootstrap mode problems • Variations for specific versions of M68HC11 • Commented listings for selected M68HC11 bootstrap ROMs © Freescale Semiconductor, Inc., 2005. All rights reserved. AN1060 Rev. 1.1, 07/2005 ...
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Basic Bootstrap Mode Basic Bootstrap Mode This section describes only basic functions of the bootstrap mode. Other functions of the bootstrap mode are described in detail in the remainder of this application note. When an M68HC11 is reset in bootstrap ...
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Bootstrap mode can also be used to interactively calibrate critical analog sensors. Since this calibration is done in the final assembled system, it can compensate for any errors in discrete interface circuitry and cabling between the sensor and the analog ...
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Boot ROM Firmware The alternate vector locations are achieved by simply driving address bit A14 low during all vector fetches if SMOD = 1. For special test mode, the alternate vector locations assure that the reset vector can be fetched ...
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Figure 2 shows how the bootloader program differentiates between the default baud rate (7812 baud at a 2-MHz E-clock rate) and the alternate baud rate (1200 baud at a 2-MHz E-clock rate). The host computer sends an initial $FF character, ...
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Main Bootloader Program [6] $FF CHARACTER START BIT 0 @ 7812 BAUD Rx DATA SAMPLES [1] $FF CHARACTER @ 1200 BAUD Rx DATA SAMPLES ( FOR 7812 BAUD ) [7] Figure 2. Automatic Detection ...
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However, such measures are not usually considered good programming technique because they are misleading to someone trying to understand the program or use example. ...
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Main Bootloader Program Figure 3. MC68HC711E9 Bootloader Flowchart 200 FROM RESET [1] START IN BOOT MODE INITIALIZATION TOP OF RAM ($01FF START OF REGS ($1000) SPCR = $20 (SET DWOM BIT) BAUD = $A2 (÷ 4; ...