MCM69R736CZP5 Motorola, MCM69R736CZP5 Datasheet

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MCM69R736CZP5

Manufacturer Part Number
MCM69R736CZP5
Description
4M Late Write HSTL
Manufacturer
Motorola
Datasheet

Specifications of MCM69R736CZP5

Case
QFP
4M Late Write HSTL
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM69R818C
(organized as 256K words by 18 bits) and the MCM69R736C (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
BiCMOS technology.
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control sig-
nals. Read data is also driven on the rising edge of CK.
(V ref ) and output voltage (V DDQ ) gives the system designer greater flexibility in
optimizing system performance.
the entire word.
match the impedance of the circuit traces which reduces signal reflections.
REV 1
8/10/99
MOTOROLA FAST SRAM
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1999
The MCM69R736C/818C is a 4M–bit synchronous late write fast static RAM
The differential clock (CK) inputs control the timing of read/write operations of
The RAM uses HSTL inputs and outputs. The adjustable input trip–point
The synchronous write and byte enables allow writing to individual bytes or
The impedance of the output buffers is programmable, allowing the outputs to
Byte Write Control
Single 3.3 V +10%, –5% Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Asynchronous Output Enable
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM69R736C/818C–4 = 4 ns
MCM69R736C/818C–4.4 = 4.4 ns
MCM69R736C/818C–5 = 5 ns
MCM69R736C/818C–6 = 6 ns
Sleep Mode Operation (ZZ pin)
119–Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array
(PBGA) Package
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MCM69R736C
MCM69R818C
MCM69R736C MCM69R818C
Order this document
by MCM69R736C/D
ZP PACKAGE
CASE 999–02
PBGA
1

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MCM69R736CZP5 Summary of contents

Page 1

... Telecom, and other high speed memory applications. The MCM69R818C (organized as 256K words by 18 bits) and the MCM69R736C (organized as 128K words by 36 bits) are fabricated in Motorola’s high performance silicon gate BiCMOS technology. The differential clock (CK) inputs control the timing of read/write operations of the RAM ...

Page 2

... DQa DQa NC V ref ref DDQ DQa SBa DQa DDQ DQa DQa TDI TCK TDO NC V DDQ MOTOROLA FAST SRAM ...

Page 3

... For More Information On This Product, MOTOROLA FAST SRAM Symbol Type CK Input Address, data in, and control input register clock. Active high. CK Input Address, data in, and control input register clock ...

Page 4

... Supply Core Power Supply. V DDQ Supply Output Power Supply: Provides operating power for output buffers. V ref Supply Input Reference: Provides reference voltage for input buffers Supply Ground. NC — No Connection: There is no connection to the chip. Go to: www.freescale.com Description MOTOROLA FAST SRAM ...

Page 5

... – – – For More Information On This Product, MOTOROLA FAST SRAM Symbol Value Unit V DD –0 DDQ –0 0 –0 0 out ...

Page 6

... 0 – 0.2 V. Min Max Unit Notes 0.3 V –0.3 V ref – 0 — –0 0 0.6 1 MOTOROLA FAST SRAM ...

Page 7

... I OL 100 100 A. CAPACITANCE (f = 1.0 MHz 3 3.3 V +10%, –5%, Characteristic Input Capacitance Input/Output Capacitance CK, CK Capacitance For More Information On This Product, MOTOROLA FAST SRAM Symbol Min DDQ /2) / [(RQ/ DDQ /2) / [(RQ/ DDQ – 0.2 ...

Page 8

... Notes — 6 — ns — 2.4 — ns — 2.4 — ns — 1 — 2.5 — — 1 — 2.5 — — 0.5 — ns 2.5 — — 0.5 — ns 2.5 — — — 200 — ns — 0.5 — ns — 1 — ns TIMING LIMITS MOTOROLA FAST SRAM ...

Page 9

... the Common Mode Input Voltage, equals V TR – [(V TR – )/2]. Figure 3. Differential Inputs/Common Mode Input Voltage V DDQ V IH (ac) V ref V IL (ac For More Information On This Product, MOTOROLA FAST SRAM Symbol V IH (ac) V ref + 200 (ac) V ref (ac) V dif (ac) 400 mV ...

Page 10

... KHKH CK t AVKH t KHAX SVKH SS SW SBx KHQV DQx Q–1 For More Information On This Product, MCM69R736C MCM69R818C 10 t KHKL t KLKH KHSX t WVKH t KHWX t KHQX1 t KHQZ t KHQX t KHQX t DVKH to: www.freescale.com A4 t KHDX Q3 MOTOROLA FAST SRAM ...

Page 11

... Freescale Semiconductor, Inc. REGISTER/REGISTER READ–WRITE–READ t KHKH CK t AVKH t KHAX SBx G DQx Q–1 For More Information On This Product, MOTOROLA FAST SRAM (G Controlled) t KHKL t KLKH GHQZ t GLQX to: www.freescale.com A4 t GLQV t GHQX Q3 MCM69R736C MCM69R818C 11 ...

Page 12

... Go to: www.freescale.com MOTOROLA FAST SRAM ...

Page 13

... No write will occur, but the outputs will be deselected normal write cycle. For More Information On This Product, MOTOROLA FAST SRAM LATE WRITE The write address is sampled on the first rising edge of clock, and write data is sampled on the following rising edge. ...

Page 14

... V DD through resistor. TDO should be left uncon- nected Unless Otherwise Noted) Symbol Min 2 –0.3 I lkg — — – 0 — 2.4 Go to: www.freescale.com Max Unit Notes 0 — 0 — MOTOROLA FAST SRAM ...

Page 15

... THTL t MVTH TEST MODE SELECT (TMS) t DVTH TEST DATA IN (TDI) TEST DATA OUT (TDO) For More Information On This Product, MOTOROLA FAST SRAM Unless Otherwise Noted 3.0 V Output Test Load 1 V/ns (20% to 80%) 1.5 V Test Load Termination Supply Voltage ( 1.5 V Symbol t THTH ...

Page 16

... TDO pins when the controller is moved into shift–DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator Bit No. 0 Value 1 Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1–1990 Bit No Value 0 0 Reserved For Future Use Bit No ...

Page 17

... ZQ, M1 and M2 are not ordinary inputs and may not respond to standard I/O logic levels. ZQ, M1 and M2 must be driven to within 100 supply rail to ensure consistent results must remain during boundary scan to ensure consistent results. For More Information On This Product, MOTOROLA FAST SRAM MCM69R818C Bump/Bit Scan Order Bump Bit ...

Page 18

... TDI and TDO when the TAP controller is moved to the shift–DR state. THE DEVICE SPECIFIC (PRIVATE) INSTRUCTION not use these instructions; they are reserved for future use. Go to: www.freescale.com MOTOROLA FAST SRAM ...

Page 19

... RUN–TEST/ IDLE 0 NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. For More Information On This Product, MOTOROLA FAST SRAM Description to High–Z state. NOT IEEE 1149.1 COMPLIANT. to High–Z state. Description SELECT DR–SCAN ...

Page 20

... ORDERING INFORMATION (Order by Full Part Number) 69R736C MCM 69R818C Tape and Reel, Blank = Tray Speed ( ns, 4.4 = 4.4 ns ns, Package (ZP = PBGA) MCM69R818CZP4 MCM69R736CZP4R MCM69R818CZP4.4 MCM69R736CZP4.4R MCM69R818CZP5 MCM69R736CZP5R MCM69R818CZP6 MCM69R736CZP6R PACKAGE DIMENSIONS ZP PACKAGE BUMP PBGA CASE 999–02 b 119X 0 0. ...

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