CY7C331-25PC Cypress Semiconductor Corporation., CY7C331-25PC Datasheet
CY7C331-25PC
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CY7C331-25PC Summary of contents
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... UV-erasable and reprogrammable — Programming and operation 100% testable Functional Description The CY7C331 is the most versatile PLD available for asyn- chronous designs. Central resources include twelve full D-type flip-flops with separate set, reset, and clock capability. For in- creased utility, XOR gates are provided at the D-inputs and the product term allocation per fl ...
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... The reason for this placement and du- al-ground structure is to minimize the ground-loop noise when the outputs are driving simultaneously into a heavy capacitive load. I/O The CY7C331 has twelve I/O macrocells (see Figure 1 ). Each 3 I/O 4 macrocell has two D-type flip-flops. One is fed from the array, ...
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... If the C2 bit is programmed, then the input comes from the lower macrocell (B). The timing diagrams for the CY7C331 cover state register, in- put register, and various combinational delays. Since internal clocks are the outputs of product terms, all timing is from the transition of the inputs causing the clock transition ...
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... CC IN Outputs Open V = Max., Outputs Disabled CC (in High Z State) Device Operating at f External (f MAX MAX1) Test Conditions MHz 2. MHz OUT 4 CY7C331 Ambient Temperature + 10% – +125 C 5V 10% Min. Max. Unit 2.4 V 0.5 V 2.2 V 0.8 V –10 ...
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... 0. 0. 0.5V (c) Test Waveforms and Measurement Levels ) [2] Description [7] [8] [8] [8] [8] [8] 5 CY7C331 ALL INPUT PULSES 90% 10 190 2.02V=V OUTPUT thm C331– C331– C331– C331– C331– C331– ...
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... Refer to Figure 3 , configuration 9. 13. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C331. This specification is met for the devices noted operating at the same ambient temperature and at the same power supply voltage. These parameters are tested periodically by sampling of production product ...
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... [12, 13] [9] [9] [9] [9] [9] [9] [9] [9] [9] [9] [14, 15] [14, 15] [14, 15] [14, 15] 25.0 33.3 [9] , 1/( 1/( [13, 18] [10, 17] 28.0 7 CY7C331 Military –25 –30 –40 Max. Min. Max. Min. Max ...
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... Refer to Figure 3 , configuration [20 [19] t IOH t [19] [21] ICO t [21] PD [22 PZX t OAR t ORW t IAR t IRW OSR 8 CY7C331 [23 ORR OSR [21 ORR OSR t ORR t OAS t OSR t OSW t IRR t t IAS ISR ...
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... TERM ARRAY SET CLOCK/S/R INPUT PRODUCT TERM ARRAY PRODUCT TERM ARRAY OUTPUT REGISTER D Q PRODUCT TERM CLOCK ARRAY Figure 3. Timing Configurations 9 CY7C331 PIN OE I/O PIN PIN OE I/O PIN PIN I/O PIN RESET OUTPUT ENABLE PIN I/O PIN OUTPUT ENABLE PIN I/O PIN I/O PIN PIN ...
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... CLOCK CLOCK INPUT PIN PIN Q OE PRODUCT TERM ARRAY CLOCK 331 OUTPUT REGISTER PIN PIN CLOCK Figure 3. Timing Configurations (continued) 10 CY7C331 PIN INPUT REGISTER PIN C331–20 330 OR 332 INPUT REGISTER D Q 330 OR 332 INPUT REGISTER D Q C331– ...
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... CY7C331 Logic Diagram (Upper Half) 11 CY7C331 ...
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... CY7C331 Logic Diagram (Lower Half) 12 CY7C331 ...
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... CY7C331–25HC CY7C331–25JC CY7C331–25PC CY7C331–25WC 150 CY7C331–30DMB CY7C331–30HMB CY7C331–30LMB CY7C331–30QMB CY7C331–30TMB CY7C331–30WMB 150 CY7C331–40DMB CY7C331–40HMB CY7C331–40LMB CY7C331–40QMB CY7C331–40TMB CY7C331–40WMB Package Name Package Type ...
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... 10, 11 IAR t 9, 10, 11 IAS t 9, 10, 11 PXZ t 9, 10, 11 PZX Document #: 38–00066–D 14 CY7C331 ...
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... Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D– 15Config.A 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C–4 28-Lead Plastic Leaded Chip Carrier J64 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C–4 15 CY7C331 ...
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... Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier 16 CY7C331 ...
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... Package Diagrams (continued) 28-Lead (300-Mil) Molded DIP P21 28-Lead Windowed Cerpack T74 17 CY7C331 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D– 15Config.A CY7C331 ...