AD8382ACP Analog Devices, AD8382ACP Datasheet

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AD8382ACP

Manufacturer Part Number
AD8382ACP
Description
Manufacturer
Analog Devices
Datasheet

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PRODUCT FEATURES
High accuracy, high resolution voltage outputs
Fast settling, high voltage drive
High update rates
Voltage controlled video reference (brightness) and
Flexible logic
Output overload protection
Low static power dissipation: 743 mW
3.3 V logic, 9 V to 18 V analog supplies
Available in 48-lead 7 mm × 7 mm LFCSP
APPLICATIONS
LCD analog column driver
PRODUCT DESCRIPTION
The AD8382 DecDriver provides a fast, 12-bit latched decimat-
ing digital input that drives six high voltage outputs.12-bit input
words are sequentially loaded into six separate, high speed,
bipolar DACs. A flexible digital input format allows several
AD8382s to be used in parallel for higher resolution displays.
STSQ synchronizes sequential input loading, XFR controls
synchronous output updating, and R/L controls the direction of
loading as either left-to-right or right-to-left. Six channels of
high voltage output drivers drive to within 1.3 V of the rail. The
output signal can be adjusted for dc reference, signal inversion,
and contrast for maximum flexibility.
The AD8382 is fabricated on Analog Devices’ XFHV, fast
bipolar 26 V process, providing fast input logic bipolar DACs
with trimmed accuracy and fast settling, high voltage, precision
drive amplifiers on the same chip. The AD8382 dissipates
743 mW nominal static power. The STBY pin reduces power to
a minimum, with fast recovery.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
12-bit input resolution
Laser trimmed outputs
33 ns settling time to 0.25% into 200 pF load
Slew rate 390 V/µs
Outputs to within 1.3 V of supply
Fast, 120 Ms/s data update rate
full-scale (contrast) output levels
STSQ/XFR allow parallel AD8382 operation
INV bit reverses polarity of video signal
Includes STBY function
High Performance 12-Bit, 6-Channel Output,
FUNCTIONAL BLOCK DIAGRAM
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
DB(0:11)
STBY
STSQ
BYP
CLK
XFR
E/O
R/L
Decimating LCD DecDriver
VREFHI
AD8382
12
SEQUENCE
CONTROL
BIAS
Figure 1. Functional Block Diagram
VREFLO
12
© 2003 Analog Devices, Inc. All rights reserved.
12
12
12
12
12
12
CONTROL
2-STAGE
2-STAGE
2-STAGE
2-STAGE
2-STAGE
2-STAGE
SCALING
LATCH
LATCH
LATCH
LATCH
LATCH
LATCH
12
12
12
12
12
12
DAC
DAC
DAC
DAC
DAC
DAC
INV
V1
www.analog.com
AD8382
V2
VID0
VID1
VID2
VID3
VID4
VID5
®

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AD8382ACP Summary of contents

Page 1

... Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...

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AD8382 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Timing Characteristics..................................................................... 6 Pin Configuration and Functional Descriptions.......................... 7 Typical Performance Characteristics ............................................. 8 Functional Description .................................................................. 13 Transfer Function ....................................................................... 13 Accuracy ...................................................................................... 14 REVISION HISTORY Revision 0: Initial ...

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SPECIFICATIONS Table 1. @ 25°C, AVCC = 15.5 V, DVCC = 3 otherwise noted. Parameter 1 VIDEO DC PERFORMANCE VDE VCME ∆V ∆V VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling ...

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AD8382 Parameter 1 REFERENCE INPUTS V1 Range V2 Range V1 Input Current V2 Input Current VREFLO Range VREFHI Range (VREFHI – VREFLO) Range VREFHI Input Resistance VREFLO Bias Current VREFHI Input Current VFS Range POWER SUPPLY DVCC, Operating Range DVCC, ...

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ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Parameter Supply Voltages AVCCx to AGNDx DVCC to DGND Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltage 2 Internal Power Dissipation LFCSP ...

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AD8382 TIMING CHARACTERISTICS Table 3. Timing Parameters and Conditions Parameter t Data Setup Time 1, t Data Hold Time 2, t STSQ Setup Time 3, t STSQ Hold Time 4, t XFR Setup Time 5, t XFR Hold Time 6, ...

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PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS Table 4. Pin Function Descriptions Mnemonic Function DB(0:11) Data Input CLK Clock STSQ Start Sequence R/L Right/Left Select E/O Even/Odd Select XFR Data Transfer VID0–VID5 Analog Outputs V1,V2 Reference Voltages VREFHI, Full-Scale References VREFLO INV ...

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AD8382 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 0.75 0.50 0.25 0.00 7V –0.25 –0.50 –0.75 –1.00 –1.25 –1.50 – 100 TIME (ns) Figure 7. Output Settling Time (Rising Edge 200 pF Step, INV ...

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TIME (ns) Figure 13. Invert Switching Step Response (Rising Edge Step 200 TIME (ns) Figure 14. Data Switching Step Response (Rising Edge Step, C =200 pF, INV = ...

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AD8382 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 512 1024 1536 2048 2564 INPUT CODE Figure 19. Differential Nonlinearity (DNL) vs. Code, INV = LOW 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 512 1024 ...

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VDE 0 VCME –1 –2 –3 –4 0 1.0 2.0 3.0 4.0 V2 – V1 (V) Figure 25. Normalized VDE, VCME vs. (V2 – V1) at Code 2048 –5 – ...

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AD8382 7. 7.04 7.03 7.02 7.01 (VID4 – VID5) 7.00 6.09 VID0 6.08 6.07 6.06 6.05 TIME (ns) Figure 31. All-Hostile Crosstalk at C 800 700 600 500 10% TO 90% 400 ...

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FUNCTIONAL DESCRIPTION The AD8382 is a system building block designed to directly drive the columns of LCD microdisplays of the type popularized for use in projection systems. It comprises six channels of precision, 12-bit digital-to-analog converters loaded from a single, ...

Page 14

AD8382 Accuracy To best correlate transfer function errors to image artifacts, the overall accuracy of the AD8382 is defined by three parameters: VDE, VCME, and ∆ V. VDE , the differential error voltage, measures the difference between the rms value ...

Page 15

APPLICATIONS OPERATING MODES—6-CHANNEL SYSTEMS Depending on the speed of the LCD microdisplay, 6-channel systems are compatible with up to XGA resolutions and require one AD8382 per color. The input/output timing diagram of the AD8382 in such systems is shown in ...

Page 16

AD8382 IMAGE PROCESSOR STSQ2 STSQ1 Pixel CLK CLK ÷6 COUNTER CLK H. REVERSE CLK ÷6 COUNTER CLK HSTART HSYNC INV1 INV2 VSYNC REFERENCES Figure 40. Single Data Bus 12-Channel Even/Odd System Block Diagram IMAGE PROCESSOR D(0:9) Odd D(0:9) Even Pixel ...

Page 17

VBIAS Generation—V1, V2 Input Pin Functionality In order to avoid image flicker, a symmetrical ac voltage is required and a bias voltage of approximately 1 V minimum must be maintained across the pixels of HTPS LCDs. The AD8382 provides two ...

Page 18

AD8382 Power Supply Sequencing As indicated in the Absolute Maximum Ratings, voltage at any input pin cannot exceed its supply voltage by more than 0 ensure compliance with these ratings, the following power- up and power-down sequencing is ...

Page 19

AD8382 PCB DESIGN RECOMMENDATIONS Land pattern Dimensions Pad Size: 0.5 mm × 0.25 mm Pad Pitch: 0.5 mm Thermal Pad Size: 5.25 mm × 5.25 mm LAND PATTERN – TOP LAYER Thermal via structure: Figure 46. Land Pattern—Top Layer 0.25 ...

Page 20

AD8382 Layout Considerations The AD8382 is a mixed-signal, high speed, high accuracy device. In order to fully realize its specifications essential to use a properly designed printed circuit board. LAYOUT AND GROUNDING The analog outputs and the digital ...

Page 21

... Although the AD8382 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Ordering Guide Table 6. Model Temperature Range AD8382ACP 0°C to 85°C 7.00 BSC SQ 0.60 MAX 37 36 6.75 ...

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AD8382 Rev Page ...

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Rev Page AD8382 ...

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... AD8382 © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. Printed in the U.S.A. C03371-0-2/03(0) Rev Page ...

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