CY7C1367A-166AJC Cypress Semiconductor Corporation., CY7C1367A-166AJC Datasheet
CY7C1367A-166AJC
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CY7C1367A-166AJC Summary of contents
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... Commercial 570 10 • 3901 North First Street • San Jose Chip Enable input is only available for 2 and CY7C1367A/ 7C1366A-166/ 7C1366A-150/ 71256C36-6 71256C36-6.7 7C1367A-166/ 7C1367A-150/ 71512C18-6 71512C18-6.7 3.0 3.5 3.5 510 425 380 • ...
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... D Q BYTE d WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER CLR D Q Binary Counter & Logic [1] BYTE b WRITE D Q BYTE a WRITE D Q ENABLE Input Register Address Register OUTPUT REGISTER D Q CLR Binary Counter & Logic 2 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 DQa,DQb DQc,DQd DQa,D Qb ...
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... DQa DQb DQb DQb CCQ 4 CCQ DQb DQb DQb DQb 8 DQb 72 DQb CCQ 11 CCQ DQb 69 DQb 12 DQb 68 DQb CY7C1367A/GVT71512C18 (512K x 18 DQa DQb TA Package Version 18 DQa 62 DQb CCQ 20 CCQ DQa 59 DQb 22 DQa 58 DQb 23 DQa 57 DQb 24 DQa CCQ 27 CCQ DQa DQa 52 NC ...
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... DQc J V CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb CCQ CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 119-Ball BGA Top View 256Kx36 ADSP ADSC DQc DQc DQc DQc BWc ADV BWb DQc DQd V CLK DQd ...
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... Mode: This input selects the burst sequence. A LOW on this Static pin selects Linear Burst HIGH on this pin selects Interleaved Burst. ZZ Input- Snooze: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC (No Connect). 5 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description ...
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... All synchronous inputs must meet setup and hold times around the clock’s rising edge. CE Input- Chip Enable: This active LOW input is used to enable the de- Synchronous vice and to gate ADSP . 6 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description Description ...
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... IEEE 1149.1 test output. LVTTL-level output. Not available for TA package version. V Supply Core power Supply: +3.3V –5% and +10 Ground Ground: GND I/O Supply Output Buffer Supply: +2.5V or +3.3V. CCQ Connect: These signals are not internally connected. User can leave it floating or connect CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description ...
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... ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 ) Burst Address Table (MODE = GND) ...
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... The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (V when the BYPASS instruction is executed. 9 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 BWb BWc BWd ...
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... EXTEST is an IEEE 1149.1 mandatory public instruction executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds SAMPLE/PRELOAD instruction has been loaded ...
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... IDLE Note: 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram 11 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- [11] ...
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... OLC [13, 15 100 A OHC [13 8.0 mA OLT [13 8.0 mA OHT (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 0 Selection Circuitry [12] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –30 30 –5.0 5 ...
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... Capture Hold CH Notes: 16. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register 17. Test conditions are specified using the load in TAP AC Test Conditions. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 [16, 17] Over the Operating Range Description 13 Min. Max Unit 20 ns ...
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... xxxxxx xxxxxx xxxxx xxxxxx xxxxxx xxxxx xxxxxx xxxxxx xxxxx xxxxxx xxxxxx xxxxx xxxxxx xxxxxx xxxxx xxxxxx xxxxxx xxxxx 14 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 ALL INPUT PULSES 1.5V 1 xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxxx ...
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... IEEE 1149.1 PRELOAD function and is therefore not 1149.1-compliant. Do not use these instructions; they are reserved for future use. Do not use these instructions; they are reserved for future use. Places the bypass register between TDI and TDO. This instruction does not affect device operations. 15 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Description Description ...
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... DQb 74 23 DQb 75 24 DQb 78 25 DQb 79 26 DQb ADV 83 30 ADSP 84 31 ADSC BWE CLK 89 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Boundary Scan Order (256K x 36) Signal Bit# Name Bump BWa 3T 38 BWb 4T 39 BWc 5T 40 BWd DQc 6M 46 DQc 7L 47 DQc 6K 48 DQc ...
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... DQa 68 14 DQa 69 15 DQa 72 16 DQa 73 17 DQa ADV 83 22 ADSP 84 23 ADSC BWE CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Boundary Scan Order (512K x 18) Signal Bit# Name Bump ID 27 CLK BWa 3T 30 BWb DQb 6N 36 DQb 6L 37 DQb 7K 38 DQb DQb 7G 41 DQb ...
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... MAX; CLK frequency = 0 CC Device deselected; all inputs < > Max CLK cycle time > t Min. KC Description Test Conditions MHz 3. CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Ambient [18] Temperature 3.3V –5%/+10% Min. Max. 2.0 V +0.3 CC 2.0 4.6 –0.5 0.8 –5 5 –30 30 –5 5 2.4 0.4 3 ...
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... Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x 1.125 inch, Thermal Resistance (Junction to Case) AC Test Loads and Waveforms for 3. 1.5V t (a) AC Test Loads and Waveforms for 2. 1.25V t (a) CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Test Conditions 4-layer PCB 317 3. 351 1.0 ns (b) 2. Symbol TQFP Typ. Unit 25 C ...
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... KQHZ KQLZ OEHZ 20 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 -5 -6 -6.7 166 MHz 150 MHz Max. Min. Max. Min. Max. 6.0 6.7 2.4 2.6 2.4 2.6 3.0 3.5 3.5 3 ...
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... OELZ xxx xxx xxxx xxx xxx xxxx Q(A1) Q(A2) Q(A2+1) xxx xxx xxxx SINGLE READ , and CE are active CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 xxxxxx xxxxx xxxxx xxxxx xxxxxx xxxxx xxxxx xxxxx xxxxxx xxxxx xxxxx xxxxx xxxxxx xxxxx xxxxx xxxxx xxxxxx xxxxx xxxxx xxxxx xxxxxx ...
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... OEHZ xxxxxxxxx xxxxxxxxx D(A1) D(A2) D(A2+1) D(A2+1) xxxxxxxxx BURST WRITE 22 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxx xxxxxx xxxxx xxxxxx xxxxx xxxxx ...
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... Q(A1) xxx Q(A2) D(A3) Single Reads Single Write 23 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxx xxxxxxxxx xxxxxxxxx xxxxxxxxx A5 xxxxxxxxx xxxxxxxxx xxxxx xxxxx ...
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... GVT71256C36TA-6 CY7C1366A-166BGC/ GVT71256C36B-6 150 CY7C1366A-150AJC/ GVT71256C36T-6.7 CY7C1366A-150AC/ GVT71256C36TA-6.7 CY7C1366A-150BGC/ GVT71256C36B-6.7 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Package Name Package Type A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead 1.4 mm Thin Quad Flat Pack BG119 119-Lead BGA ( 2.4 mm) A101 100-Lead 1.4 mm Thin Quad Flat Pack A101 100-Lead ...
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... Speed (MHz) Ordering Code 225 CY7C1367A-225AJC/ GVT71512C18T-4.4 CY7C1367A-225AC/ GVT71512C18TA-4.4 CY7C1367A-225BGC/ GVT71512C18B-4.4 200 CY7C1367A-200AJC/ GVT71512C18T-5 CY7C1367A-200AC/ GVT71512C18TA-5 CY7C1367A-200BGC/ GVT715152C18B-5 166 CY7C1367A-166AJC/ GVT715152C18T-6 CY7C1367A-166AC/ GVT71512C18TA-6 CY7C1367A-166BGC/ GVT71512C18B-6 150 CY7C1367A-150AJC/ GVT71512C18T-6.7 CY7C1367A-150AC/ GVT71512C18TA-6.7 CY7C1367A-150BGC/ GVT71512C18B-6.7 Document #: 38-01011-*B CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 Package Name Package Type A101 100-Lead ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 26 51-85050-A ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead BGA ( 2.4 mm) BG119 CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 51-85115 ...