CY7C1313V18-250BZC Cypress Semiconductor Corporation., CY7C1313V18-250BZC Datasheet
CY7C1313V18-250BZC
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CY7C1313V18-250BZC Summary of contents
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... Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311V18) or 18-bit words (CY7C1313V18) or 36-bit words (CY7C1315V18) that burst sequentially into or out of the device. Since data can be transferred into and out of the ...
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... Logic Block Diagram (CY7C1313V18) D [17:0] 18 Address Register A (17: CLK K Gen. DOFF V REF WPS Control Logic BWS [1:0] Logic Block Diagram (CY7C1315V18) D [35:0] 36 Address Register A (16: CLK K Gen. DOFF V REF WPS Control Logic BWS [3:0] Selection Guide Maximum Operating Frequency Maximum Operating Current Document #: 38-05181 Rev ...
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... TCK A Document #: 38-05181 Rev. *D CY7C1311V18 (2M × 8)–11 × 15 FBGA NC/144M BWS K WPS 1 A NC/288M K BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1313V18 (1M × 18)–11 × 15 FBGA NC/288M WPS BWS BWS DDQ DDQ DDQ DDQ DDQ DDQ DDQ CY7C1311V18 CY7C1313V18 CY7C1315V18 ...
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... These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized arrays each of 512K x 8) for CY7C1311V18 arrays each of 256K x 18) for CY7C1313V18 and 512K arrays each of 128K x 36) for CY7C1315V18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311V18, 18 address inputs for CY7C1313V18 and 17 address inputs for CY7C1315V18 ...
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... C and C clocks during Read operations or K and K. when in single clock mode. When the Read port is deselected, Q tri-stated. CY7C1311V18 − Q CY7C1313V18 − Q CY7C1315V18 − Q RPS Input- Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a Read operation is initiated ...
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... Each access consists of four 8-bit data transfers in the case of CY7C1311V18, four 18-bit data transfers in the case of CY7C1313V18, and four 36-bit data in the case of CY7C1315V18 transfers in two clock cycles. Accesses for both ports are initiated on the Positive Input Clock (K) ...
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... The above application shows four QDRII being used. Document #: 38-05181 Rev. *D Depth Expansion The CY7C1313V18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). ...
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... D [8: written into the device. D [7: written into the device. D [17: written into the device. D [7: written into the device. D [17:9] ↑ represents rising edge. , BWS in the case of CY7C1311V18 and CY7C1313V18 and also 0 1 CY7C1311V18 CY7C1313V18 CY7C1315V18 D K(t D ↑ K(t +2) ↑ ...
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... D will remain unaltered. [26:0] – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. CY7C1311V18 CY7C1313V18 CY7C1315V18 ) are written [35:0] ) are written [35: written [8:0] ...
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... CYC IL − (Max 0.2V. IL REF (min.) within 200ms. During this time V < V and (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1311V18 CY7C1313V18 CY7C1315V18 Ambient [16] [16 DDQ 1.8 ± 0.1V 1. Min. Typ. Max. 1.7 1.8 1.9 1.4 1 ...
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... AC test loads and t less than t . CLZ CHZ CO CY7C1311V18 CY7C1313V18 CY7C1315V18 200 MHz 167 MHz Min. Max. Min. Max. Unit 5.0 6.3 6.0 8.4 ns – 2.0 2.4 – ns – ...
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... MHz 1. 1.5V DDQ V = 0.75V REF V 0.75V R = 50Ω REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250 Ω (b) CY7C1311V18 CY7C1313V18 CY7C1315V18 165 FBGA Package Unit 16.7 °C/W 2.5 °C/W Max. Unit [14] ALL INPUT PULSES 1.25V 0.75V Slew Rate = Page [+] Feedback ...
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... READ WRITE KHKH D10 D11 D12 Q00 Q01 Q02 CLZ t DOH KHKH t CCQO t CQOH t CCQO t CQOH CY7C1311V18 CY7C1313V18 CY7C1315V18 NOP 7 6 D30 D31 D32 D33 D13 Q03 Q20 Q21 Q22 Q23 t DOH t CHZ t CQD t CQDOH DON’T CARE UNDEFINED Page [+] Feedback ...
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... Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document #: 38-05181 Rev. *D CY7C1311V18 CY7C1313V18 CY7C1315V18 TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section ...
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... Document #: 38-05181 Rev. *D CY7C1311V18 CY7C1313V18 CY7C1315V18 The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. ...
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... IDLE Note: 26. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05181 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1311V18 CY7C1313V18 CY7C1315V18 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... Over the Operating Range Test Conditions = −2 −100 µ 2 100 µ GND ≤ V ≤ [28,29] Over the Operating Range Description / ns CY7C1311V18 CY7C1313V18 CY7C1315V18 Selection TDO Circuitry Min. Max. Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD µA –5 5 Min ...
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... Over the Operating Range Description [29] 1. TCYC t TMSS t TMSH t TDIS t TDIH t TDOV Value CY7C1313V18 CY7C1315V18 000 000 00000110100 00000110100 1 CY7C1311V18 CY7C1313V18 CY7C1315V18 Min. Max. Unit ALL INPUT PULSES 0.9V t TDOX Description Version number. Allows unique identification of SRAM vendor. 1 Indicates the presence register. Page [+] Feedback ...
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... Boundary Scan Order Bit # 11P 31 10P 32 10N 10M 35 11N 11L 39 11M 10L 42 11K 43 CY7C1311V18 CY7C1313V18 CY7C1315V18 Description affect the SRAM operation. (continued) Bump ID 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C Page [+] Feedback ...
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... Boundary Scan Order (continued) Bit # Bump Document #: 38-05181 Rev. *D Boundary Scan Order Bit # 9B 88 10B 89 11A 90 Internal 100 5B 101 5A 102 4A 103 5C 104 4B 105 3A 106 CY7C1311V18 CY7C1313V18 CY7C1315V18 (continued) Bump Page [+] Feedback ...
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... Ordering Information Speed (MHz) Ordering Code 250 CY7C1311V18-250BZC CY7C1313V18-250BZC CY7C1315V18-250BZC 200 CY7C1311V18-200BZC CY7C1313V18-200BZC CY7C1315V18-200BZC 167 CY7C1311V18-167BZC CY7C1313V18-167BZC CY7C1315V18-167BZC Package Diagram QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT,NEC, and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders. ...
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... Document History Page Document Title: CY7C1311V18/CY7C1313V18/CY7C1315V18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 38-05181 ISSUE ORIG. OF REV. ECN NO. DATE CHANGE DESCRIPTION OF CHANGE ** 110860 11/09/01 *A 115918 08/01/02 *B 201266 See ECN *C 206681 See ECN *D 218050 See ECN Document #: 38-05181 Rev. *D SKX ...