CXA3106AQ Sony, CXA3106AQ Datasheet
CXA3106AQ
Related parts for CXA3106AQ
CXA3106AQ Summary of contents
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... PLL IC for LCD Monitor/Projector Description The CXA3106AQ is a PLL IC for LCD monitors/ projectors with built-in phase detector, charge pump, VCO and counter. The various internal settings are performed by serial data via a 3-line bus. Applicable LCD monitor/projector resolution are NTSC, PAL, VGA, SVGA, XGA, and SXGA etc. ...
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... PECLV , IRV CC CC –0. level IOV 1 L level 2 H level 2 L level – 2 – CXA3106AQ –0.5 to +7.0 –0.5 to +0.5 IOGND – 0.5 to IOV + 0.5 CC IRGND – 0.5 to IRV + 0.5 CC –30 to +30 – –65 to +150 –25 to +75 750 Min. Typ. Max. 4.75 5 ...
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... CXA3106AQ ...
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... IREF analog power supply CC Reference voltage level 5V 0V PECL PECL TTL TTL PECL PECL TTL TTL TTL TTL TTL TTL TTL TTL TTL 5V 0V TTL TTL TTL TTL TTL PECL PECL PECL PECL PECL PECL PECLV – 1. 1.3V 1.7 to 4.4V 2. – 4 – CXA3106AQ ...
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... VCO circuit analog GND. VCO SUB analog GND. IREF analog GND. IREF analog power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. – 5 – CXA3106AQ Description ...
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... IOGND – 6 – CXA3106AQ Description External VCO input. Programmable counter test input (switchable by a control register). When using the VCO PECL input, open the Pin 5 VCO TTL input. External inverted VCO input. When open, this pin goes to the PECL threshold voltage (IOVcc – 1.3V). ...
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... Control Register Table and Control Timing Chart.) Programmable counter test input. This pin is normally open status and high. Register contents can be loaded immediately to Programmable counter by setting TLOAD low during the programmable counter test mode. – 7 – CXA3106AQ Description ...
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... I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance control register. Delay sync signal output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) and switched between positive/negative polarity by a control register. – 8 – CXA3106AQ Description ...
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... IOGND – 9 – CXA3106AQ Description Unlock signal output. This pin is an open collector output, and pulls in the current when a phase difference occurs. The UNLOCK sensitivity can be adjusted by connecting a capacitor and resistors to this output as appropriate. (See the UNLOCK Timing Chart.) TTL output can be turned ON/OFF (high impedance control register ...
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... CC VCOV VCOGND IRGND 100 IOGND – 10 – CXA3106AQ Description PECL reference voltage. When used, ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. Charge pump current preparation. Connect to GND via an external resistor (1.6k ). Ground this pin to the ground pattern with a 0.1µ ...
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... CXA3106AQ ...
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... IOV – 0.8V –100 IOV – 1.6V –200 2.7V –200 0.5V –500 PECLV 330 –1 330 RL = 330 CL = 10pF 2 10pF – 12 – CXA3106AQ (Ta = 25° 5V, GND = 0V) CC Typ. Max. Unit 70 105 IOV CC V –1.5 IOV CC V –1.3 100 µA 0 µA V 0.8 V – ...
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... DIV = 1/4 10 1.7 DIV = 1/1 240 DIV = 1/2 120 DIV = 1/4 60 C.Pump Bit = 00, 80 IREF = 1.6k C.Pump Bit = 10, 350 IREF = 1.6k C.Pump Bit = 11, 1350 IREF = 1.6k – 13 – CXA3106AQ Typ. Max. Unit mA 100 kHz 2 bit 4 CLK 5 bit 20/16 CLK 160 MHz 80 MHz ...
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... RL = 330 DIV = 1/1 40 DIV = 1/2 20 DIV = 1/4 10 10% to 90%, 2 10pF 10% to 90%, 2 10pF CL = 10pF 10pF CL = 10pF 1 10pF 0 10pF 10pF 10pF 1.5 – 14 – CXA3106AQ Typ. Max. Unit 160 MHz 80 MHz 40 MHz 1.5 2.0 ns 1.5 2 MHz 80 MHz 40 MHz 3.0 4.0 ns 3.0 4.0 ...
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... Fclk = 136.00MHz N = 1700 triggered at DSYNC in write/read mode in write mode 3 in write mode 0 in write mode 3 in read mode 0 in read mode 3 in read mode 0 – 15 – CXA3106AQ Typ. Max. Unit 5.0 8.0 ns 2.0 3.0 ns 1.6 2.5 ns 1.5 2.0 ns 1.0 1 ...
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... PD POL = 1. Phase comparison is performed at the edges. The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped at the front end of the CXA3106AQ when inputting a noisy signal. The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.) The PLL UNLOCK signal is output by an open collector ...
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... ON OFF OFF 1 0 OFF ON 00001 · · · · · · · · · · · · 2/16CLK · · · · · · · · · · · · 2CLK 3CLK 1 0 Negative – 17 – CXA3106AQ 10011 20/16CLK 11 4CLK ...
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... REGISTER7 REGISTER7 REGISTER7 H L All OFF 1 0 Control registers only Function ON – 18 – CXA3106AQ 12bit VCO DIV Bit0 to 11 2bit DIV1 Bit0, Bit1 5bit FINE DELAY Bit0 to 4 2bit COARSE DELAY Bit0, Bit1 2bit C.Pump Bit0, Bit1 1bit PD POL 1bit SYNC POL ...
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... VCO input (during test mode) This is the programmable counter test signal input pin. This pin can be switched internally by the MUX circuit. TTL and PECL input are possible. This pin is normally not used. Register: VCO By-pass Input status Internal VCO Function External input – 19 – CXA3106AQ ...
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... Control Register Timing 1) Write mode Many CXA3106AQ functions can be controlled via a program. Characteristics are changed by setting the internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin 11) and SDATA (Pin 12). The write timing diagram is shown below. Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but the data is input aligned with the LSB side in these cases ...
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... DIVREG2 (upper 4 bits of VCODIV) CENFREREG (2 bits of DIV1 DIVREG1 (lower 8 bits of VCODIV) All three of the above registers must be changed even when changing only DIV1 bits). This is the same when changing only VCODIV (12 bits). SENABLE SDATA SCLK DIVREG2 CENFREREG DIVREG1 – 21 – CXA3106AQ ...
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... I/P SHIFT REGISTER, 11 BITS 8 BIT DATA 3 BIT ADDRESS 7 DATA REGISTERS (41 LATCHES). REGISTERS ARE DIFFERENT LENGTHS BIT SCAN PATH, 1 ELEMENT PER REGISTER BIT Block Diagram during Read Mode READ NO. 1 READ NO Timing Chart during Read Mode – 22 – CXA3106AQ SEROUT TNENH READ NO ...
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... Thh Ths Thold The phase comparison output is held and fixed VCO output frequency is output 1nA 1ms 0.33µF, and KVCO = 2 · 65MHz, then: leak hold –6 – [V] – · 197 [Hz] – 24 – CXA3106AQ Thh Ths ...
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... Therefore follows. 1. DSYNC = L when SYNC = L and DIVOUTN = L. 2. DSYNC = (unchanged with the previous data) when SYNC = H and DIVOUTN = L. 3. DSYNC = H when DIVOUTN = H (SYNC = SYNC DIVOUTN and ( ) are unchanged with the previous data. DSYNC Q internal signal – 25 – CXA3106AQ is the impossible DSYNC ...
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... DSYNC output (DSYNC POL = 0) 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK 8CLK 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK – 26 – CXA3106AQ 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK 8CLK 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK ...
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... DSYNC output (DSYNC POL = 0) 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK – 27 – CXA3106AQ 1/fSYNC 1/fSYNC 1/fSYNC Ths Thh 8CLK 8CLK 8CLK 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK ...
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... DSYNC internal signal DSYNC output (DSYNC POL = 0) 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK – 28 – CXA3106AQ 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK 1/fSYNC 1/fSYNC 1/fSYNC Thh Ths 8CLK 8CLK 8CLK ...
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... Also, if the resistance R2 is increased, the S2 signal rise slew rate becomes slower. If this integrated S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes from low to high, and the PLL is said to be unlocked UNLOCK Inside the IC Outside the unlock I1 detect – 29 – CXA3106AQ R2 UNLOCK C threshold level threshold level threshold level ...
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... KPD is A/rad. Also, when considering the VCO input as a voltage, the LPF transmittance dimension must be expressed in ohms ( = V/A). Therefore, the PLL transmittance when a constant-current output charge pump circuit is used is as follows. LPF PD KPD F (S) (A/rad counter 1 ... (1) (A/rad (rad/sV) – 30 – CXA3106AQ VCO 0 KVCO (rad/sV) ...
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... Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3106AQ's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants ...
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... The filter transmittance is as follows · R · ( (( · C2 · R · · ( · · · C2 · Here, assuming C2 = C1/100, then: C1 · C1/100 · C1/100 · R 101 101 Vo The Bode diagram for formula ( follows. .................. (7) –90 – 32 – CXA3106AQ log w log w 0 –45deg ...
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... Next, the various parameters inside an actual CXA3106AQ are obtained. The CXA3106AQ's charge pump output block and the LPF circuit are as follows 100µA or 400µA or 1600µA 100µA or 400µA or 1600µA First, KPD is as follows. KPD = 100µ/2 or 400µ/2 or 1600µ/2 Typical KVCO characteristics curves for the CXA3106Q's internal VCO are as follows ...
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... CXA3106AQ setting µF kHzrad kHz 780 0.33 3300 2.51 0.40 1.37 1170 0.33 3300 4.10 0.65 2.23 1560 0.33 3300 3.55 0.57 1.93 940 0.33 3300 2.29 0.36 1 ...
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... CLK Jitter Evaluation Method The regenerated CLK is obtained by applying Hsync to the CXA3106AQ. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger. Hsync Pulse Generator H Sync Computer signal Hsync CLK Enlarged Trigger The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure ...
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... Jitter peak-peak vs Output Frequency NTSC/PAL, DIV = 1/ VGA, DIV = 1/ SVGA, DIV = 1/ XGA, DIV = 1/ SXGA, DIV = 1/ 100 120 Output Frequency [MHz] – 36 – CXA3106AQ K Temperature characteristics VCO Ta = +75° +25° –25°C 2.0 2.5 3.0 3.5 4.0 4.5 VCO Control Voltage [V] Fine Delay Td2 vs Fine Delay Bit Ta = – ...
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... Ground the power supply pins of the IC with a 0.1µF or larger ceramic chip capacitor as close to each pin as possible. • Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during high-speed operation. • Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3106AQ PWB.) – 37 – CXA3106AQ ...
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... The loop filter's capacitors and resistor should also be temperature compensated. PECL level output pins 330 Control Register HOLD SYNCH, SYNCL: PECL level complementary input – 38 – CXA3106AQ 25 DSYNC 24 CLK 23 CLKN 22 CLK/2 21 CLK/ DGND 100k UNLOCK output 100 UNLOCK 17 10nF DIVOUT 16 GND ...
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... The loop filter's capacitors and resistor should also be temperature compensated Control Register HOLD SYNC: TTL level input – 39 – CXA3106AQ 25 TTL level output pins DSYNC 24 CLK 23 CLKN 22 CLK/2 21 CLK/2N 20 DGND 100k 100 UNLOCK output UNLOCK 17 10nF DIVOUT ...
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... When connecting the PLL output to A/D converters with built-in demultiplex function such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured by connecting the CLK (PECL) and CLKN (PECL) outputs of the CXA3106AQ to the CLK (PECL) and CLKN (PECL) inputs of each A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3106AQ to the RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively ...
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... See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.) • Within the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3106AQ vs. A/D converter 1/2 clock output The setup time is T–3ns and the hold time is T–5ns. CXA3106AQ ...
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... Connecting the CXA3106AQ with Sony ADC (Straight Mode) When connecting the PLL output to A/D converters such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured as shown below. Wiring Diagram PLL CXA3106AQ VIN CLK (PECL) TTL CLKN (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q VIN CLK (PECL) ...
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... See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.) • Within the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3106AQ vs. clock output from CXA3106AQ The setup time is T–4.5ns and the hold time is 1.5ns. CXA3106AQ ...
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... CXA3106AQ-PWB (CXA3106AQ Evaluation Board) The CXA3106AQ-PWB is an evaluation board for the CXA3106AQ PLL-IC. This board makes it possible to easily evaluate the CXA3106AQ's performance using the supplied control program (Note: IBM PC/AT, MS- DOS 5.0 and newer US mode specifications). Features • Two input level (TTL and PECL) SYNC input • ...
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... PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective control registers. Therefore, the enable/disable settings should be made in accordance with the application. See the following pages for the setting method. – 45 – CXA3106AQ ...
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... Power Save, connect the jumper wire to S5 (CS = low). (For the initial setting, the jumper wire is connected to S6.) Supplied Program This PWB is equipped with a control program that facilitates evaluation of the CXA3106AQ. Operation methods and precautions are as follows. 1) Compatible personal computers Use an IBM PC/AT or compatible machine equipped with a 25-pin D-SUB parallel port (printer port). Also, operating systems which support the program are MS-DOS 5 ...
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... Use Pg Up and increment/decrement divisor and fine delay registers. Press a to abort scan registers CXA3106 PLL REGISTERS Divisor 1344 Divider 2 Fine Delay Charge Pump 10 Power SCAN SYNTH OFF ON DSYNC CLK2 NCLK2 OFF OFF OFF MIXED SIGNAL SYSTEMS JAN 1997 – 47 – CXA3106AQ 10 VCO Bypass ON CLK1 NCLK1 OFF OFF ...
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... Return or Enter key. (Note: The operating range of the CXA3106AQ is from 256 to 4096.) The value can also be incremented or decremented by one step by pressing the Page Up or Page Down key, respectively. ...
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... VCO Bypass: This is set to OFF when testing the program counter. This should normally be set to ON. O/P Enable These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2, NCLK2, CLK1 and NCLK1). Set to ON when performing evaluation using TTL output. – 49 – CXA3106AQ ...
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... C) Description of readout mode This program has a function (readout mode) that reads the contents written to the control registers from the CXA3106AQ SEROUT (Pin 15) and displays these contents on the screen. This function is described below. 1) Set SCAN the function setting screen. 2) Press the S key. ...
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... Substrate Pattern (parts surface) Substrate Pattern (solder surface) – 51 – CXA3106AQ ...
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... Silk Screen (solder surface) – 52 – VCC GND C21 33µ + PR10 VBB R1 R8 PR8 PR9 DSYNCL DSYNCH R3 R2 R10 R9 PR6 PR7 CLKL CLKH R7 R4 R14 R11 PR1 PR5 CLK/2L CLK/ R13 R12 PR12 PR13 PR14 PR15 CLK/2 CLKN CLK DSYNC CXA3106AQ ...
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... M + 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT – 54 – CXA3106AQ + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g Sony Corporation ...