W88113CF Winbond, W88113CF Datasheet
W88113CF
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W88113CF Summary of contents
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W88113C ATAPI CD-ROM Decoder & Controller ...
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... These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Version ...
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OVERVIEW .............................................................................................................1 1.1 FEATURES ...........................................................................................................................................1 1.1.1 Host Interface ...................................................................................................................................1 1.1.2 DSP Interface....................................................................................................................................1 1.1.3 Microcontroller Interface ..................................................................................................................1 1.1.4 DRAM Interface ...............................................................................................................................2 1.1.5 Audio Playback Interface ..................................................................................................................2 1.1.6 Miscellaneous ...................................................................................................................................2 1.2 BLOCK DIAGRAM..............................................................................................................................3 1.3 PIN CONFIGURATION .......................................................................................................................4 1.4 PIN DESCRIPTION..............................................................................................................................5 1.5 ...
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MICROCONTROLLER INTERFACE..............................................................................................80 5.2.1 Direct Register Addressing .............................................................................................................80 5.2.2 General I/O.....................................................................................................................................81 5.2.3 Programmable System Clock ..........................................................................................................81 5.3 HOST INTERFACE............................................................................................................................83 5.3.1 Ultra DMA Mode Setting................................................................................................................83 5.3.2 Ultra DMA Data-out.......................................................................................................................83 5.3.3 Ultra DMA Error Handling.............................................................................................................84 5.3.4 Ultra DMA Data-In Transfer Diagram............................................................................................84 5.3.5 ...
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ATAPI CD-ROM DECODER & CONTROLLER 1. OVERVIEW 1.1 Features 1.1.1 Host Interface Support ATAPI CD-ROM standard (SFF 8020) Ultra DMA/33 support to achieve high throughput and data integrity 32-byte Data FIFO to increase data throughput Support Block-offset transfer and Linear ...
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DRAM Interface Various DRAMs support (128K x 8, 256K 64K x 16, 128K x 16, 256K x 16) Supports ring-control-register to add flexibility of DRAM control FPG/EDO DRAM support Programmable DRAM timing Programmable refresh ...
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Block Diagram Sync Detector & DSP Descrambler Real Time EDC Parallel ECC Corrector & EDC Micro- Microprocessor Processor Smart DRAM Bandwidth Subcode Arbitrator Interface 32 Bytes Data FIFO Checker Interface Checker 12 Bytes Command Interface Packet FIFO - 3 ...
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Pin configuration GND RA3 CASH RD11 RD12/ALE1 ABCK RD14 LRCK SDATA BCK C2PO RD15/DJ CLKO/ALRCK XOUT XIN GND SCSB WFCK SCSYN EXCK HRSTb/GIO1 UD0 UD1 RD13 UD2 UD3 UD4 UD5 UD6 GND ...
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Pin Description The following convention is used in the pin description table below: (I) denotes an input (O) denotes an output (OZ) denotes a tri-state output (OD) denotes an open-drain output (I/O) denotes a bi-directional signal Miscellaneous Pins NAME ...
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Audio Interface NAME NO. ABCK 6 CLKO/ALRCK 13 46 ACLK ASD0 58 ROEB/ASD1 84 86 RD8/ASD2 Host Interface NAME NO. TYPE 54, 56, 59, 62, DD[15:0] I/OZ 65, 68, 70, 73, 74, 71, 69, 67, 63, 61, 57, 55 DA[2:0] ...
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DSP Interface NAME NO. TYPE LRCK 8 I SDATA 9 I SDATA1 72 I BCK 10 I C2PO 11 I Subcode Interface NAME NO. TYPE SCSD 17 I WFCK 18 I SCSYN 19 I EXCK 20 I/O External RAM Interface ...
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Pin Table NO. NAME TYPE 1 GND P 2 RA3 O 3 CASH O 4 RD11 I/O 5 RD12/ALE1 I/O 6 ABCK O 7 RD14 I/O 8 LRCK I 9 SDATA I 10 BCK I 11 C2PO I 12 ...
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Pin Table, continued NO. NAME TYPE 31 UD7 I/O 32 URS/DAO/GIN3 I/O 33 URDb I 34 UWRb I 35 UCSb I 36 UINTb OD 37 DASPb I/OD 38 CS3b I 39 CS1b I 40 DA2 I 41 VDD P ...
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Pin Table, continued NO. NAME TYPE 61 DD2 I/O 62 DD12 I/O 63 DD3 I/O 64 ALE2 I 65 DD11 I/O 66 GND P 67 DD4 I/O 68 DD10 I/O 69 DD5 I/O 70 DD9 I/O 71 DD6 I/O ...
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Pin Table, continued NO. NAME TYPE 91 RD10/RA9 I/O 92 RA8 O 93 RA7 O 94 RD9 I/O 95 RA6 O 96 RA5 O 97 RA4 O 98 RA0 O 99 RA1 O 100 RA2 O 1.6 Definitions Asserted/Activated: ...
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Decrement/Increment: Decrement means that a value minus 1. Increment means that a value plus 1. Negated/De-activated: Negated and de-activated mean that a signal is driven to its false state. Sector: This term refers to the data contained by one frame ...
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REGISTERS DESCRIPTION IR - Index Register (read/write) If DRA (5Bh.1) is high, the Index Register is latched at the falling edge of pin ALE1 (5) or pin ALE2 (64) depending on the setting of ALE2 (5Ch.3). If DRA (5Bh.1) ...
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Bits Reserved Bit 1: DTEN - Data Transfer Enable Set this bit high enables the data transfer logic. This bit should be set before trigger any data transfer. In order to reduce the interference of microprocessor, this ...
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Bit 4: HCIb - Host Command Interrupt Flag This bit is activated by the following events: Host issues ATAPI Soft Reset Command, if ARSTIEN(2Fh.1) is enabled Host issues command to a non-exist slave drive, if SHIEN(2Eh.2) is enabled Host issues ...
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TWCL - Transfer Word Counter Low- (read/write 02h) Before triggering data transfer, the number of words to be transferred should be set through 12-bit Transfer Word Counter (TWC). The number of words minus 1 should be written to this counter ...
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TACK - Transfer Acknowledge - (write 07h) Writing this register deactivates flag TENDb (01h.r6) and its corresponding interrupt regardless of what data is written. HEAD0 to HEAD3 - Header Registers - (read 03h to 07h) These four registers are used ...
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EIAL/EIAH - ECC Initial Address - (read 08h/09h, write 0Ch/0Dh) EIAH/L are used to hold the initial address offset of the data block to be corrected. The content of BIAH/L (09h/08h,w) will be automatically loaded to EIAH/L at the beginning ...
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DECEN BUFEN EDCEN 0Ah.7 0Ah.2 0Ah Note that if ATMSEN (9Ah.6) is high, the decoder logic will operate in Disk-monitor mode before ...
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Bit 1: MCRQ - Mode Byte Check Request When this bit is high, ECC logic will check the 4th header byte with the setting of M2RQ (0Bh.3) to determine if ECC correction to be performed. Bit 0: SHDEN - Subheader ...
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SIEN Status Flag (0Bh.7) x ILSYN(0Ch.6) NOSYN(0Ch. LBKF(0Ch.4) SBKF(0Ch.2) x Bit 1: reserved Bit 0: UEBK - Uncorrectable Errors in Block This bit is used to indicate that at least one data is corrected in the latest available ...
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DHTACK - DRAM to Host Transfer Acknowledge - (write 0Eh) Writing DHTACK, regardless of what data is written, deactivates TENDb (01h.r6) that caused by data- in transfer. STAT2 - Status Register 2 - (read 0Eh) Bit 7-4: RMOD[3:0] - Raw ...
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FRST - Firmware Reset Register - (write 0Fh) Writing this register, regardless of what value is written, trigger a firmware reset. Flag FRST (2Fh.r1) is set by firmware reset. STAT3 - Status Register 3 - (read 0Fh) Bit 7: STAVAb ...
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Bit 1: DRST - Decoder Reset Setting this bit to high resets decoding logic, including: SRIEN (01h.w5) CTRL0 (0Ah,w) 00h CTRL1 (0Bh,w) 00h CTRLW (10h,w) STAT0-2 (0Ch-0Eh,r) STAT3 (0Fh,r) 80h TARSTA (80h,r) DRST is automatically cleared by itself. CRTRG - ...
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MBTC0 - Multi-Block Transfer Control 0 - (read/write 12h) The host interface supports multi-block transfer without microprocessor intervention by following sequence: MBC (12h.4-0) the number of block to be transferred minus 1 (ex. 3) TWCH/L (03h/-2h) 1175) TACH/L (05h/04h) TBH/L ...
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Bit 7: MBVAb - Multi-Block Counter Valid Flag This bit is used to indicate that MBC (12h.4-0) is stable enough to be monitored by microprocessor. There is no need to monitor this bit in normal operation. Bit 6: MBINC - ...
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Bit 0: DISAI - Disable Auto-Increment of Microprocessor-RAM Address Counter When this bit is high, the automatic increment of the RAC (2Dh/1Dh/1Ch) address counter is disabled. Note that DISAI should be 0 before RFTRG (2Ah.w6) is triggered. SUBH0 to SUBH3 ...
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Bit 3: CPFT - Clear Packet FIFO Trigger Setting this bit high clears the Packet FIFO. Bit 2: ADTT - Automatic Data Transfer Trigger If PIO (1Fh.2) is high, setting ADTT high triggers the following PIO Data Transfer sequence: Set ...
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Clear BSY HIRQ (2Eh.3) 1 APKTEN (18h.7) ASCEN (18h.5) After detecting the interrupt, the host reads the ATAPI Status Register and if necessary, the Error Register for the command completion status. ASCTRL - Automatic Sequence Control register - (read/write 18h) ...
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Writing any value to register TACK (07h) deactivates APKT, TENDb, and corresponding interrupt. Bit 6: ADCEN - Automatic DRQ Clearing Enable When this bit is high, DRQ (37h.3) is cleared to 0 and BSY (37h.7) is set to 1 after ...
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Bit 2: AUCRCEN - Automatic Ultra DMA CRC Error Logic Enable If AUCRCEN (18h.2) is set high, the automatic status complete logic would be stopped if UCRCOKB (30h.r3) is high CRC error has occurred in last Ultra DMA ...
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CCTL1 - Clock Control Register 1 - (write 1Ah) This register is 0 after chip reset. Bit 7: CLKOEN Setting this bit high enable pin CLKO (13) as clock output if APOUT (90h.1-0) is zero. CLKOEN (1Ah. ...
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DSPSL - DSP Selection Register - (write 1Bh) Bit 7: C2ML - C2 MSB to LSB When this bit is high, the sequence of erasures via pin C2PO (11) is from MSB to LSB. Bit 6: S16O - Select 16 ...
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RAMWR - RAM Write Register - (write 1Eh) To gain access to external RAM, the microprocessor should first wait for flag UTBY (1Fh.r7) to become low, then set the address through RACLU/H/L(2Df/1Dh/1Ch). Writing data into register RAMWR triggers the following ...
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Bit 0: UDMA - Ultra DMA Enable Setting this bit high selects data transfer protocol as Ultra DMA. The bandwidth of Ultra DMA depends on the system frequency and the setting of UDT1-0 (8Ah.5-4). PIO mode MDMA mode UDMA mode ...
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Chip reset or Host reset This bit is also controlled by DASPS2 (3Fh.2), DASPS1 (3Fh.1) and DASPSS (3Fh.0). Bit 4: CLRBSY - Clear BSY Setting this bit high causes the flag BSY in the ATAPI Status Register to become low ...
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SCIACK - Subcode Interrupt Acknowledge - (write 22h) Writing any value to this register de-activates SCIb (01h.r0) if SCIEN (2CH.w4) is enabled. SUBSTA - Subcode Status Register - (read 22h) When SCIb (01h.r0) is activated, the microprocessor can read this ...
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SCBH/L - Subcode Block Register - (read/write 27h/26h) SCBH/L (27h/26h) form a 9-bit counter that contains the block number of the latest available subcode data that can be read by the host. The number in SCBH/L (27h/26h) plus 1 points ...
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Bit 5: Reserved (write only) Bit 4: SWAP - Host High-Low Swap Setting this bit high causes the host access of high/low byte to be swapped. Bit 3: Reserved Bit 2-0: RTC[2:0] - External RAM Type Configuration Bits The external ...
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Bit 1-0: RLC[1:0] - External RAM Layout Configuration Bits The memory layout configuration should be set as shown in the following table: RLC[1:0] 0 The block size should be set as C00h if C2WEN (10h.w2) is enabled. SICTL1 ...
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MISC0 - Miscellaneous Control Register 0 - (write 2Eh) Bit 7: HIIEN - Host Interface Interrupt Enable Setting this bit high enables the microprocessor interrupt of the host interface. Host interface interrupt occurs at the following conditions: SRST (Device Control ...
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MISS0 - Miscellaneous Status Register 0 - (read 2Eh) Bit 5: SRUb - Status Register Updated Flag This bit becomes high when the ATAPI Status Register is updated by the following: Microprocessor writes to 37h Microprocessor triggers DSCT (17h.w5) Microprocessor ...
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Bit 5-4: HRSTS[1:0] - HRSTb Pin Function Select HSTS[1] HSTS[ Bit 3-2: ARSTS[1:0] - ARSTb Pin Function Select ARSTS[1] ARSTS[ When ARSTS1 is high, ...
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Disable pin DASPb (37) to high-impedance state if DASPSS (3Fh.0) is low. Negates pin DASPb (37) if DASPSS (3Fh.0) is high. CKSTP (19h.7) Activates host interrupt to the microprocessor if HIIEN (2Eh.w7) is high. HIRQ (2Eh.w3) 0 Host interrupt is ...
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Bit 4: SHDC - Shadow Command Flag This bit becomes high when the host writes a command to a non-existent slave drive. Meanwhile, pin UINTb (36) becomes low-active if SHIEN (2Eh.w2) is enabled. ATAC is de- activated by the following: ...
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Bit 6: CMDC - Command Conflict This bit becomes high if one of the following events occurs while BSY is high: Host writes any opcode to ATAPI Command Register while drive is selected. Host writes any opcode to ATAPI Command ...
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ATERR - ATAPI Error Register (write 31h/read 39h) This register is set as 01h by the following events: Chip reset or host reset SRST Execute Drive Diagnostics Command Triggering SIGT (17h.w4) ATFEA - ATAPI Feature Register (read 31h) This register ...
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ATBLO - ATAPI Byte Count Low (read/write 34h) This register is set as 14h by chip reset, host reset, SRST or triggering SIGT (17h.w4). This register is set as 00h by Execute Drive Diagnostics Command. ATBHI - ATAPI Byte Count ...
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ASERR - ATAPI Shadow Error Register - (write 39h) Bit 2: SABRT - Shadow ABRT Bit The microprocessor should set SABRT following each host write to ATCMD to comply with ATAPI specification if configured as a master drive. The other ...
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SHDCTL - Shadow Drive Control Register (read/write 3Fh) Bit Reserved Bit 6: SHDRV - Shadow Drive Enable If MDRV (2Fh.4) is high, the bit reflects the level on pin DASPb (43) until SHDRVL (3Fh.5) is set high. ...
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Ring Control Registers - (read/write 50h to 57h) These eight registers add flexibility to the block control of external memory that is controlled by RTC2-0 (2Ah.2-0) initially. Once one of these eight registers is set, all eight registers should be ...
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PSKCTL - Programmable System Clock Control Register - (read/write 59h) This register should be set before the programmable system clock is enabled by setting PSKEN (1Ah.w4) high. This register is 0 after chip reset. Bit 7: PSKSEL (write) - Programmable ...
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... This alternative power-on setting provides a way to do conventional indirect register addressing. Bit 0: Reserved Power-On Setting of Register Addressing Mode The default register addressing mode of W88113CF is direct register addressing mode. Alternative Power-On Setting RA8 pull-down RA7 pull-down 4 ...
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Bit 1: reserved Bit 0: RMSRI - Remove Frequent SRIb If RMSRI (5Ch.0) is high, flag SRIb (01h.r5) is generated only by flags STAERR (80h.r6), DSFULI (80h.r4), LASTBK (80h.r3), LTTI (80h.r2), TNFI (80h.r1) or HCEI (80h.r0). Setting this bit high ...
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TARCTL - Target Control Register - (write 80h) This register is used to control the automatic target search and header comparison. Since these control bits are not changed by closing decoder, there is no need to write it before every ...
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TARSTA - Target Status Register - (read 80h) This register is 0 after chip reset, host reset, firmware reset and decoder reset. Reading this register deactivates SRIb (01h.r5). Bit 7: TARGED - Target Is Found This bit is high after ...
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DSTL - Decoding Sector Threshold Register - (write 81h) If DSCEN (80h.w6) is enabled, this register specified the threshold number of successive sectors minus one to be decoded after header is targeted. Flag DSFULI (80h.r4) becomes high when value in ...
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TARGET0 - Target Minute Register - (read/write 84h) TARGET1 - Target Second Register - (read/write 85h) TARGET2 - Target Frame Register - (read/write 86h) DACTL - Digital Audio Control Register - (read/write 87h) This register is 00h after chip reset ...
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Bit 3: SBCK - Select BCK as subcode clock When this bit is high, the pin BCK (10) is selected as subcode reference clock instead of system clock. This setting is suitable for drive using CAV subcode. Bit 2: CAS8B ...
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DFFCNTL - Data FIFO Threshold Control Register - (read/write 89h) Bit 7,6: Reserved Bit 5-3: DFFHT[2:0] - Data FIFO High Threshold When the number of bytes in Data FIFO larger than DFFHT, device stops pre-fetch to prevent FIFO overrun. Since ...
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Bit 5-4: UDT[1:0] - Ultra DMA Timing Control These two bits define the Ultra DMA Timing Factor, udtf, which control the timing of Ultra DMA transfer. Tcyc = ( 2 + udtf ) Tudma where Tudma is clock period that ...
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STA1M - Status 1 Mask Register - (write 8Dh) If any following bit is enabled, the flag STAERR (80h.r6) becomes high when the corresponding status bit becomes active. Bit 4: HDERA Mask Bit 0: SHDER Mask STA2M - Status 2 ...
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Bit 5: APDIRECT - Audio Direct Playback Setting this bit high directs the original DSP signals to the audio playback pins. Bit 4: APINS - Audio Reference Input Select If this bit is set low, pin ACLK (46) is used ...
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APFMT4 APFMT3 ALRCK ABCK 15 ADAT ALRCK ABCK ADAT ALRCK ABCK ADAT 0 15 ALRCK ABCK ADAT PHILIPS Audio Format ...
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APWCL/H - Audio Playback Word Count Register - (read/write 94h/95h) The number in this counter plus one is the word count to be playbacked for each memory block. The default value of these registers is 0497h after chip reset, host ...
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PUCTL - Pull Up Resistor Control Register - (write 98h) This register is used to control the utilization of two pull-up resistors on IO cells. Default value is 0. Bit 7-6: HIP[1:0] - Host Interface Pull-up Control Setting these two ...
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BICCTL - Buffer Independent Correction Control Register - (read/write 9Ah) This register is 0 after chip reset, host reset and firmware reset. Bit 7: BICEN - Buffer Independent Correction Enable If this bit is high, the buffer-independent-correction (BIC mode) is ...
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ACCTL - Automatic Cache Control Register - (read/write 9Ch) This register is 0 after chip reset, host reset and firmware reset. Bit 7: ATTEN - Automatic Transfer Trigger Enable The control bit ADTT (17h.w2) is automatically set high if all ...
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SKIPC - Skip Count - (read/write 9Eh) This register is used as skip count to implement a partial-hit event of transfer cache. If ACMEN (9Ch.6) is high, the following functions are executed right after SKIPC (9Eh) is set N: BUFC ...
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REGISTER TABLE Note that this table is MSB leading. INDEX TYPE name bit7 - r/w IR index 00h r PFAR b7 01h w INTCTL pfneen 01h r INTREA pfne 02h r/w TWCL b7 03h w TWCH latxf 03h r ...
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ASTRG 0 18h r/w ASCTRL apkten 19h w CCTL0 ckstp 1Ah w CCTL1 clkoen 1Ah r VER E6h 1Bh w DSPSL c2ml 1Bh r C2BEB b7 1Ch w RACL a7 1Dh w RACH a15 2Dh w RACU 0 ...
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ASERR 0 39h r ATERR b7 3Ah r LDDBL latched DDBL 3Bh r LDDBH latched DDBH 3Dh w APKSTA 0 3Eh w ASCSTA 0 3Fh r/w SHDCTL 0 48h r LSTA0 crcok 49h r LSTA1 0 4Ah r ...
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STA0M crcokm 8dh w STA1M 0 8eh w STA2M 0 8fh w STA3M 0 90h r/w APCNF apen 91h r/w APFMT apfmt7 92h r/w APBKL b7 93h r/w APBKH aptest 94h r/w APWCL 97h 95h r/w APWCH 04h ...
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CHARACTERISTICS ( 5 SYM PARAMETER V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH1 V Input LOW Voltage IL1 V Input ...
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APPLICATION NOTES 5.1 DRAM Interface 5.1.1 Memory Layout The whole DRAM can be divided into Sector Data Area and Working Area. Sectors from DSP are buffered into Sector Data Area and then are retrieved for ECC/EDC operation. Some information ...
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Block Configuration The configuration of each memory block depends on the data format. The following figures show the recommended configuration of block whose size is A00h and C00h, respectfully. 9FFh Header (4) Sync (12) 9F0h Unused (16) 9E0h Subcode ...
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The rule for configuration is that the first byte of the sector is stored at: BIAH/L(09h/08h,w) - 0Ch And the following byte is stored into the incremented offset address. If the offset address reaches the block limit, the next offset ...
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Linear Address v.s. Block-Offset Address The microprocessor can write/read external RAM through register RAWR/RAMRD (1Eh) based on linear address defined by RACU/H/L (2Dh/1Dh/1Ch,w). DRAM to host can base on block-offset address or linear address. The following equation defines the ...
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TWCH/L (03h/02h) as 008Fh set TACH/L (05h/04h) as 0800h Case 3: The 2352 bytes of sync, header, user data and EDC&ECC are request by host. set TBH/L (25h/24h) as 001Fh set TWCH/L (03h/02h) as 0497h set TACH/L (05h/04h) as ...
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... DRAM Timing 5.2 Microcontroller Interface 5.2.1 Direct Register Addressing The default register addressing mode of W88113CF is direct register addressing mode. If ALE2 (5Ch.3) is low, pin RD12/ALE1 (5) is used as ALE input; otherwise, pin ALE2 (64) is used as ALE input (default after chip reset). Alternative Power-On Setting ...
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General I/O Pin HRSTb (21) and pin ARSTb (60) can be configured as general I/O pins through register MISC1 (2Fh,w). The state of these two general I/O pins can be controlled through register GIOCTL (5Fh). The pin state of ...
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XIN=33.86MHz, PSKCTL (59h) = D3h, CCTL1 (1Ah) = 98h <example> XIN=33.86MHz, PSKCTL (59h) = D5h, CCTL1 (1Ah) = 98h Publication Release Date: Mar. 1999 - 82 - W88113C Revision 0.61 ...
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Host Interface The host interface is a standard ATAPI interface with enhanced Ultra DMA support. The Ultra DMA protocol could double the current burst transfer rate of 16.6MB/sec to 33MB/sec without hardware changes such as termination devices or different ...
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TWCH/L (03h/02h) should be set 4 instead of 5. Then firmware should repeatedly read register PFAR (00h,r) after Transfer End Interrupt asserts until flag PFNEb (01h.r7) becomes one. <example> data-out transfer sequence: 1. TENDEN (01h.w6) 2. ASCTRL (18h,w) ...
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Data-in Transfer Flowchart Example start HICTL(1Fh) = 0Ch for PIO = 08h for MDMA = 09h for UDMA ASCTRL(18h) = 44h or 74h set TWCH/L(03h/02h) set TACH/L(05h/04h) set TBH/L(25h/24h) set MBTC0(12h) set ATBHI/LO(35h/34h) ADTT(17h. return data-in trigger ...
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BSY flag control BSY is bit-7 of ATAPI Status Register. BSY set chip reset host reset Set bit SRST in ATAPT Device Control Register Set SETBSY (20h.w3) if APKT (30h.r0) is low Host issues Execute Diagnostics Command (opcode 90h) ...
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Decoder Logic 5.4.1 Sync Detection/Insertion The sync field of CD-ROM data is recorded as following: 1 (00h) bytes, 10 (FFh) bytes and 1 (00h) byte. This sync field is detected for sector synchronization if SDEN (0Bh.w6) is enabled. To ...
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EDC Checking The EDC checking logic carry 32-bit CRC checking on error corrected data according to its mode. The checking result can be monitored through flag CRCOK (0Ch.r7). If the result is error, the errors in sector may exceed ...
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SIEN (0Bh.7) CD-DA yellow book Mode 1 yellow book Mode 2 CD-ROM XA M2F1 CD-ROM XA M2F2 5.4.9 CD-DA data & Q-channel Extraction There are no sync bytes in CD-DA format, so MSF bytes of Q-channel information can ...
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Target Search The target search logic is initialized by: (1) setting Search Limit, (2) setting Target and (3) setting TARGEN (80h.w7) high. After the decoding is triggered through CTRL0 (0Ah,w), the first sector ready interrupt is generated when: i) ...
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Decoder Processing Flow DSP data T-2 Buffering decoding SRIb(01h.5) target is found BUFEN(0Ah.2) target T-1 DDBH/L (RTC) DDBH/L (BIC) Note the value that set to DDBH/L 5.4.14 Buffer-Independent-Correction Buffer-Independent-Correction (BIC) is enabled if BICEN (9Ah.7) ...
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Remove Frequent SRIb & Automatic Cache Management Control bit RMSRI (5Ch.0) should be set when entering buffer mode and be disabled in decoder_off routine. When RMSRI (5Ch.0) is high, flag SRIb (01h.r5) is generated only by STAERR (80h.r6), LASTBK ...
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TSL(83h) BICCTL(9Ah) = B0h BUFLIM(9Bh) = buf_lim set HICTL(1Fh) return ASCTRL(18h) = 74h set TWCH/L(03h/02h) decoder_ini set TACH/L(05h/04h) CTRLW(10h) = 50h ACCTL(9Ch) = 111xxxxxb yMonitor_Mode = 1 yDec_Idle = 0 set SKIPC(9Eh) decoder_on return decoder_on yMonitor_Mode? ...
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Audio-playback 5.5.1 Configuration Phase 1. Configure input/output pin for Audio-playback through APCNF (90h). - Bit 6: Audio Playback Interrupt Enable - Bit 4: Audio Reference Clock Select - Bit 3,2: Audio Input Reference Clock Setting - Bit 1:0: Audio ...
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Audio Playback Flowchart Example Play Command sctor in buffer decoder_restart no yes set APBKH/L(93h/92h) APEN(90h. return APIb(01h.2) APACK(97h) = FFh last sector in buffer < threshold no command yes APEN(90h. return Publication Release Date: Mar. ...
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... Example: The top marking of W88113CF inbond W88113CF 904AF27039530 1st line: Winbond logo 2nd line: the type number: W88113CF 3rd line: Tracking code 904: packages made in '99, week 4 A: assembly house ID; A means ASE, S means SPIL F: IC revision; D means version D, F means version F ...
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... PACKAGE DIMENSIONS W88113CF (100-pin PQFP Dimension in inches Symbol Min. Nom. Max. A 0.002 0.010 1 A 0.101 0.107 2 b 0.008 0.012 c 0.004 0.006 D 0.547 0.551 E 0.787 0.783 E e 0.026 H 0.695 0.705 D H 0.931 0.941 E L 0.031 0.025 L 0.077 W88113C Dimension in mm Min. Nom. ...
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... TLX: 16485 WINTPE Note: All data and specifications are subject to change without Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 98 - W88113C Dimension in mm Dimension in inches Symbol Min. Nom. Max. ...