LXT970AQC Intel Corporation, LXT970AQC Datasheet
LXT970AQC
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LXT970AQC Summary of contents
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... CMOS process with single 5Vsupply operation with provision for interface to 3.3V MII bus. Integrated LED drivers. Integrated supply monitor and line disconnect during low supply fault. Available in: — 64-pin TQFP (LXT970ATC) — 64-pin PQFP (LXT970AQC) o Commercial temperature range ( ambient). Order Number: 249099-001 January 2001 C ...
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... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...
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Contents 1.0 Pin Assignments and Signal Descriptions 2.0 Functional Description 2.1 Introduction..........................................................................................................18 2.2 Interfaces (Network Media/Protocol Support) .....................................................19 2.2.1 Twisted-Pair Interface ............................................................................19 2.2.2 Fiber Interface ........................................................................................19 2.2.3 MII Interface ...........................................................................................20 2.2.3.1 Selectable Driver Levels............................................................20 2.2.3.2 MII Data Interface......................................................................21 2.2.3.3 Repeater ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.8.2.3 Carrier Sense (CRS) ................................................................. 38 2.8.3 Twisted-Pair PMD Layer ........................................................................ 39 2.8.3.1 Scrambler/Descrambler (100TX Only) ...................................... 39 2.8.3.2 Baseline Wander Correction 2.8.3.3 Polarity Correction..................................................................... 39 2.8.4 Fiber PMD Layer .................................................................................... 39 2.8.5 Additional ...
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Figures 1 LXT970A Block Diagram ....................................................................................... 9 2 LXT970A Pin Assignments .................................................................................10 3 Network Interface Card (NIC) Application ..........................................................18 4 MII Interface .......................................................................................................20 5 MII Data Interface ...............................................................................................21 6 Loopback Paths ..................................................................................................23 7 Repeater Block Diagram ....................................................................................24 8 MDIO Interrupt ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Tables 1 LXT970A Power Supply Signal Descriptions ...................................................... 10 2 LXT970A MII Signal Descriptions ....................................................................... 11 3 LXT970A Fiber Interface Signal Descriptions ..................................................... 12 4 LXT970A Twisted-Pair Interface Signal Descriptions ......................................... 13 5 LXT970A ...
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Auto Negotiation Advertisement Register (Address 4)........................................67 50 Auto Negotiation Link Partner Ability Register (Address 5).................................68 51 Auto Negotiation Expansion (Address 6) ............................................................69 52 Mirror Register (Address 16, Hex 10)..................................................................69 53 Interrupt Enable Register (Address 17, Hex 11) .................................................70 54 ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Revision History Revision Date 8 Description Datasheet ...
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Figure 1. LXT970A Block Diagram TX_EN MII TX_ER TX TXD<0:4> TX_CLK MF<0:4> CFG<0:1> Hardware FDE Interface Management/ TRSTE Mode Select RESET FDS/MDINT MII MDIO MGMT MDDIS MDC Crystal Osc XTALI/O 2 RX_CLK RXD<0:4> MII RX CRS Carrier Sense Collision Detect ...
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... VCCR, NDR 24, 26 VCCA, NDA 9, 43 VCCD, GNDD 53, 52 VCCIO, GNDIO 1. Pin numbers apply to all package types. 10 Part # LXT970AQC/ATC XX XXXXXX XXXXXXXX I/O - Transmitter Supply (+5V) and Ground. (Analog plane) - Receiver Supply (+5V) and Ground. (Analog plane) - Analog Supply (+5V) and Ground. - Digital Supply (+5V) and Ground. ...
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Table 2. LXT970A MII Signal Descriptions 1 Pin# Pin Name I/O 63 TXD4 62 TXD3 61 TXD2 60 TXD1 59 TXD0 58 TX_EN 57 TX_CLK 56 TX_ER 46 RXD4 47 RXD3 48 RXD2 49 RXD1 50 RXD0 51 RX_DV 55 ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 2. LXT970A MII Signal Descriptions (Continued) 1 Pin# Pin Name 3 TRSTE 15 MDDIS 45 MDC 44 MDIO 2 FDS/MDINT 1. Pin numbers apply to all package types. 2. I/O Column Coding: I ...
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Table 4. LXT970A Twisted-Pair Interface Signal Descriptions 1 2 Pin# Pin Name I/O 21 TPOP Twisted-Pair Output, Positive and Negative. Differential driver pair produces 802.3- AO compliant pulses for either 100BASE-TX or 10BASE-T transmission. 23 TPON 20 TREF AO Transmit ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 7. LXT970A Hardware Control Interface Signal Descriptions 1 2 Pin# Pin Name I/O Multi-Function (MF). Five dual-function configuration inputs. Each pin accepts one of four input voltage levels (V A simple resistor divider ...
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Table 7. LXT970A Hardware Control Interface Signal Descriptions (Continued Pin# Pin Name I/O Full-Duplex Enable. When A/N is enabled, FDE determines full-duplex advertisement capability in combination with MF4 and CFG1. 13 FDE I When A/N is disabled, FDE ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 8 summarizes the relationship between input voltage levels (V the configuration function for each of the MF input pins. Each MF pin shows two configuration inputs; configuration function and MII address. The initial ...
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Table 9. LXT970A Auto-Negotiation Operating Speed/Full-Duplex Advertisement Settings Desired Configuration Advertise all capabilities Ignore FDE Advertise 10 Mbps only Advertise FD Advertise 10 Mbps only Do Not Advertise FD Advertise 100 Mbps only Advertised FD Advertise 100 Mbps only Do ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.0 Functional Description 2.1 Introduction The LXT970A, a new-generation version of the LXT970 10/100 PHY Fast Ethernet Transceiver incorporates several functional enhancements for a more robust Ethernet solution. The LXT970A supports optional MII driver ...
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Interfaces (Network Media/Protocol Support) The LXT970A provides the following interfaces: • A Twisted-Pair Interface which directly supports 100BASE-TX and 10BASE-T applications. • A pseudo-ECL (PECL) Fiber Interface which supports 100BASE-FX applications through an external fiber transceiver. • An MII ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver The LXT970A does not support the Signal Detect Function. However, the PMA functions of the LXT970A guarantee that it will detect invalid link conditions and break down a link, even without the Signal Detect ...
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MII Data Interface Figure 5 shows the data portion of the MII interface. Separate channels are provided for transmitting data from the MAC to the LXT970A (TXD), and for receiving data (RXD) from the line. Each channel has its ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver The LXT970A synchronizes the receive data and control signals to RX_CLK. The LXT970A always changes these signals on the falling edge of RX_CLK in order to stabilize the signals at the rising edge of ...
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Test Loopback A test loopback function is provided for diagnostic testing of the LXT970A. During test loopback the twisted-pair interface is disabled. Data transmitted by the MAC is internally looped back by the LXT970A and returned to the MAC. Test ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.2.3.3 Repeater Mode The LXT970A MII normally operates in DTE Mode (19.13 = 0). An alternative operating mode is available for repeater applications (19.13 = 1). In Repeater Mode, the Carrier Sense (CRS) and ...
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The LXT970A can signal an interrupt using the MDIO signal as shown in Figure pin 2 (FDS/MDINT) will be used as an MDINT pin. The protocol allows one controller to communicate with multiple LXT970A ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.2.4 Hardware Control Interface The Hardware Control Interface consists of MF<4:0>, CFG <1:0> and FDE input pins. This interface is used to configure operating characteristics of the LXT970A and to determine the MDIO Address. ...
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Table 14. LXT970A Operating Configurations / Auto-Negotiation Disabled 1,2 Desired Configuration Force 100FX Operation Force 100TX Operation Force 10T Operation Force Full-Duplex Operation Disable 10T Link Test Enable 10T Link Test 1. Refer to Table 12 for basic configurations. 2. ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.3.2.1 Master Clock Mode The Master Clock mode is recommended in most Network Interface Cards (NICs) and switch applications. In Master Clock mode the LXT970A is the master clock source for data transmission, and ...
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Bias Circuit Requirements A 22 resistor must be tied between the RBIAS input and ground. High-speed signals should be kept away from this resistor. Follow the layout recommendations given in the Design Recommendations section on 2.4 Initialization ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.4.2.1 Manual Configuration The LXT970A can be manually configured to force operation in the following modes: • 100FX, full-duplex • 100FX, half-duplex • 100TX, full-duplex • 100TX, half-duplex • 10T, full-duplex • 10T, half-duplex ...
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Controlling Auto-Negotiation When auto-negotiation is controlled by software, the following steps are recommended: • After a reset or power-up (initial or from power down mode), the power down recovery time (refer to Table 43 on page • Set MDIO Register ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.5.2 Monitoring Status via Indicator Pins The LEDS, LEDR, LEDT, LEDL, and LEDC pins are CMOS digital outputs that drive LEDs. These pins along with the FDS/MDINT output, can also be used to externally ...
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Network Operations During 100BASE-X operation, the LXT970A transmits and receives 5-bit symbols across the network link. Figure 13 actively transmitting data, the LXT970A sends out Idle symbols on the line. In 100TX mode, the LXT970A scrambles the data ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 17. 4B/5B Coding 4B Code Code Type ...
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Operation 2.7.1 10BASE-T MII Operations The MAC transmits data to the LXT970A over the MII interface. The LXT970A converts the digital data from the MAC into an analog waveform that is transmitted to the network via the copper ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.8.1.1 100X Preamble Handling When the MAC asserts TX_EN, the PCS substitutes a /J/K symbol pair, also known as the Start of Stream Delimiter or SSD, for the first two nibbles received across the ...
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Collision Indication Figure 18 shows normal transmission. The LXT970A detects a collision if transmit and receive are active at the same time. As shown in asserted and remains asserted for the duration of the collision. Figure 16. 100BASE-TX Reception ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.8.1.5 SQE (10T Only) When the SQE (heartbeat) function is enabled, the LXT970A asserts its COL output for 5-15 BT after each packet. By default, the SQE function is disabled on the LXT970A. To ...
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For 10T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker. The PMA layer in the LXT970A does not support the optional Far-End-Fault function. 2.8.3 Twisted-Pair PMD Layer The twisted-pair ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 2.8.5 Additional Operating Features 2.8.6 Low-Voltage-Fault Detect The LXT970A low-voltage fault detection function prevents transmission of invalid symbols when VCC goes below normal operating levels. If this condition occurs, the LXT970A disables the transmit ...
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Application Information 3.1 Magnetics Information The LXT970A requires a 1:1 ratio for both the receive and the transmit transformers. Refer to Table 18 for magnetics requirements. A cross-reference list of magnetic manufacturers and part numbers is available in Application ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 3.3 Design Recommendations The LXT970A is designed in accordance with IEEE requirements and provides outstanding receive Bit Error Ratio (BER) and long-line-length performance. Lab tests show that the LXT970A performs well beyond the required ...
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The recommended implementation is to divide the VCC plane into two sections. The digital section supplies power to the digital VCC pin, VCCIO pin, and to the external components. The analog section supplies power to VCCA, VCCT, and VCCR pins ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver 3.3.5.2 Fiber The fiber interface consists of a pseudo-ECL transmit and receive pair to an external fiber optic transceiver. The transmit pair should be AC-coupled to the transceiver, and biased to 3.7V with a ...
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Typical Application Figure 21 on page 46 pins; it does not portray the actual chip pinout. The Media Independent Interface (MII) pins are at the upper left. Hardware Control Interface pins are center left. The line interface pins for ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 21. Typical Interface Circuitry GNDD C1 TX_EN TXD<4:0> TX_ER 55 TX_CLK 55 MII COL Data 55 RX_DV I/F 55 RX_ER 55 RX_CLK 7 55 RXD<4:0> TRSTE 55 CRS MII MDIO Control FDS/MDINT I/F ...
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Test Specifications Note: Table 21 through Table 43 specifications of the LXT970A. These specifications are guaranteed by test except where noted “by design.” Minimum and maximum values listed in recommended operating conditions specified in Table 21. Absolute Maximum Ratings ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 23. Digital I/O Characteristics Parameter 3 Input Low Voltage 3 Input High Voltage Input Current Output Low Voltage Output High Voltage (MII only) Output High Voltage MII Driver Output Resistance (Line Driver Output ...
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Table 26. Low Voltage Fault Detect Characteristics Parameter Detect Fault Threshold Clear Fault Threshold 1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing. Table 27. 100BASE-TX Transceiver Characteristics ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 29. 10BASE-T Transceiver Characteristics Parameter Peak Differential Output Voltage Transmit Timing Jitter added by the 2,3 MAU and PLS Sections 2 Receive Input Impedance Differential Squelch Threshold 1. Typical values are at 25 ...
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Figure 22. MII - 100BASE-TX Receive Timing / 4B Mode TPIP CRS 1 TRSTE RX_DV RXD<3:0> RX_CLK COL Table 31. MII - 100BASE-TX Receive Timing Parameters / 4B Mode Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 23. MII - 100BASE-TX Transmit Timing / 4B Mode TXCLK TX_EN TXD<3:0> TPOP CRS Table 32. MII - 100BASE-TX Transmit Timing Parameters / 4B Mode Parameter TXD<3:0>, TX_EN, TX_ER Setup to TX_CLK High ...
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Figure 24. MII - 100BASE-TX Receive Timing / 5B Mode 0ns TPIP CRS 1 TRSTE RX_DV RXD<4:0> RX_CLK COL 1. This parameter applies only when the device is operated in Repeater Mode Repeater Mode, application circuit must assert ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 25. 100BASE-TX Transmit Timing / 5B Mode TXCLK TX_EN TXD<3:0> TPOP CRS Table 34. MII - 100BASE-TX Transmit Timing Parameters / 5B Mode Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, ...
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Figure 26. MII - 100BASE-FX Receive Timing / 4B Mode FIBIP CRS 1 TRSTE RX_DV RXD<3:0> RX_CLK COL 1. These parameters apply only when the device is operated in Repeater Mode Repeater Mode, application circuit must assert TRSTE ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 27. MII - 100BASE-FX Transmit Timing / 4B Mode 0ns TXCLK TX_EN TXD<3:0> FIBOP CRS Table 36. MII - 100BASE-FX Transmit Timing Parameters / 4B Mode Parameter TXD<3:0>, TX_EN, TX_ER Setup to TX_CLK ...
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Figure 28. MII - 10BASE-T Receiving Timing RX_CLK RXD, RX_DV, RX_ER CRS t 7F TPI t 7H COL Table 37. MII - 10BASE-T Receive Timing Parameters Parameter RXD, RX_DV, RX_ER Setup to RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 29. MII - 10BASE-T Transmit Timing TX_CLK t 8A TXD, TX_EN, TX_ER t 8C CRS TPO Table 38. MII - 10BASE-T Transmit Timing Parameters Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, ...
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Figure 30. 10BASE-T SQE (Heartbeat) Timing TX_CLK TX_EN COL Table 39. 10BASE-T SQE (Heartbeat) Timing Parameters Parameter COL (SQE) Delay after TX_EN off COL (SQE) Pulse duration 1. Typical values are at 25 °C and are for design aid only; ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 32. Auto Negotiation and Fast Link Pulse Timing Clock Pulse TPOP t1 Figure 33. Fast Link Pulse Timing FLP Burst TPOP t4 Table 41. Auto Negotiation and Fast Link Pulse Timing Parameters Parameter ...
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Figure 34. MDIO Timing when Sourced by STA MDC MDIO Figure 35. MDIO Timing when Sourced by PHY MDC MDIO Table 42. MDIO Timing Parameters Parameter MDIO Setup before MDC MDIO Hold after MDC MDC to MDIO Output delay 1. ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 36. Power-Down Recovery Timing (Over Recommended Range) VCC RESET MDIO,etc Table 43. Power-Down Recovery Timing Parameters Parameter Power-Down recovery time Hardware reset time 1. Typical values are at 25° C and are for ...
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Register Definitions The LXT970A register set includes a total of twelve 16-bit registers. Refer to complete register listing. • Seven base registers (0 through 6) are defined in accordance with the “Reconciliation Sublayer and Media Independent Interface” and “Physical ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 45. Control Register (Address 0) Bit Name 1 = Reset chip. 0.15 Reset 0 = Enable normal operation Enable loopback mode. When Loopback is enabled, during 100 Mbps operation, the LXT970A ...
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Table 46. Status Register (Address 1) Bit Name 1.15 100BASE-T4 Not Supported. 100BASE-X 1. LXT970A able to perform full-duplex 100BASE-X. full-duplex 100BASE-X 1. LXT970A able to perform half-duplex 100BASE-X. half-duplex 10 Mb/s 1. LXT970A ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 47. PHY Identification Register 1 (Address 2) Bit Name PHY ID 2.15:0 The PHY identifier composed of bits 3 through 18 of the OUI. Number Read Only Table 48. PHY ...
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Table 49. Auto Negotiation Advertisement Register (Address 4) Bit Name 4.15 Next Page Not Supported 4.14 Reserved Ignore on read Remote fault. 4.13 Remote Fault remote fault. 4.12:11 Reserved Ignore on read Pause ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 50. Auto Negotiation Link Partner Ability Register (Address 5) Bit Name 1 = Link Partner has ability to send multiple pages. 5.15 Next Page 0 = Link Partner has no ability to send ...
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Table 51. Auto Negotiation Expansion (Address 6) Bit Name 6.15:5 Reserved Ignore Parallel detection fault has occurred. Parallel 6.4 Detection Fault 0 = Parallel detection fault has not occurred Link partner is next page able. Link ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 53. Interrupt Enable Register (Address 17, Hex 11) Bit Name 17.15:4 Reserved Write as 0; ignore on read Reduced MII driver levels. Pull-down strength of the MII driver is reduced by ...
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Table 55. Configuration Register (Address 19, Hex 13) Bit Name 19.15 Reserved Write as 0; ignore on read 100BASE-T transmit test enabled, LXT970A transmits data regardless of link status. This function is the analog of the link test ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Table 55. Configuration Register (Address 19, Hex 13) (Continued) Bit Name 1 = Enable 100BASE fiber interface. 19.2 100BASE- Enable 100BASE twisted-pair interface. 19.1 Reserved Write as 0; Ignore on read. 1 ...
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... Mechanical Specifications Figure 38. 64-Pin QFP Package Diagram 64-Pin Quad Flat Pack • Part Number - LXT970AQC • Commercial Temperature Range (0 to +70º Datasheet Dual-Speed Fast Ethernet Transceiver — LXT970A Millimeters Dim Min Max A – 3.30 A 0.000 0. 2.55 3. 0.30 0.45 D 17.65 18. ...
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LXT970A — Dual-Speed Fast Ethernet Transceiver Figure 39. 64-Pin TQFP Package Diagram 64-Pin Thin Quad Flat Pack • Part Number - LXT970ATC • Commercial Temperature Range (0 to +70ºC) Millimeters Dim Min A – 0.95 2 ...