W83877F Winbond, W83877F Datasheet
W83877F
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W83877F Summary of contents
Page 1
... GENERAL DESCRIPTION One of Winbond's popular series of I/O chips, the W83877F integrates a disk drive adapter, serial port (UART), parallel port, IDE bus interface, and game port decoder onto a single chip. The W83877F is an enhanced version of the W83777F, with additional powerful features such as configurable plug-and-play registers for the whole chip and infrared support in one of the serial ports ...
Page 2
... Even, odd or no parity bit generation/detection 1, 1 stop bits generation Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simulation Programmable baud generator allows division of 1.8461 MHz and 24 MHz Parallel Port W83877F 16 -1) ...
Page 3
... JOYSTICK mode supports joystick through parallel port Others: Programmable configuration settings Immediate or automatic power-down mode for power management All hardware power-on settings have internal pull-up or pull-down resistors as default value Packaged in 100-pin QFP Configurable Plug and Play registers Infrared communication port Publication Release Date: January 1996 - 3 - W83877F Revision A2 ...
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... X 94 CS0 CS1 96 IRQ_A DACK_B X 99 IRQ_F X 100 DRQ_B W83877F RIB 50 X DCDB 49 X DSRB 48 X CTSB DTRB X 45 RTSB X 44 IRQ_C X SOUTB SINB GMRD 40 GND GMWR 38 SOUTA X 37 IRQ_D X 36 RTSA X 35 DTRA X 34 CTSA X 33 DSRA X 32 DCDA RIA ...
Page 5
... CPU I/O read signal CPU I/O write signal DMA request signal B 12t DMA Acknowledge signal B DMA request signal C 12t DMA Acknowledge signal C Terminal Count. When active, this pin indicates termination of a DMA transfer. Interrupt request input - 5 - W83877F FUNCTION Publication Release Date: January 1996 Revision A2 ...
Page 6
... UART A Serial Output. Used to transmit serial data out to the communication link. During power-on reset, this pin is pulled up internally and is defined as PIRIDE, which provides the power-on value for CR16 bit 1 (IRIDE recommended when intends to pull down at power-on reset W83877F FUNCTION FUNCTION ...
Page 7
... During power-on reset, this pin is pulled down internally and is defined as PGOIQSEL, which provides the power-on value for CR16 bit 4 (GOIQSEL pull up at power-on reset. Publication Release Date: January 1996 - 7 - W83877F is recommended when intends is recommended when intends is recommended when intends is recommended when intends Revision A2 ...
Page 8
... This input pin controls the chip power down. When this pin is active, the clock supply to the chip will be inhibited and the output pins will be tri-stated as defined in CR4 and CR6. The PDCIN is pulled down internally. Its active state is defined by bit 4 of CRA (PDCHACT). Default is high active W83877F FUNCTION ...
Page 9
... EXTENSION ADAPTER MODE: XDRQ DMA request generated by the Extension Adapter. An active high input. EXTENSION 2FDD MODE: DSB2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the DSB pin. JOYSTICK MODE: NC pin. Publication Release Date: January 1996 - 9 - W83877F Revision A2 ...
Page 10
... This pin is for Extension FDD B; its functions are the same as 12t those of the WE pin. EXTENSION ADAPTER MODE: XA1 This pin is system address A1 for the Extension Adapter. EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WE pin. JOYSTICK MODE: NC pin W83877F FUNCTION ...
Page 11
... This pin is the DMA terminal count for the Extension Adapter. The count is sent by TC directly. EXTENSION 2FDD MODE: STEP2 This pin is for Extension FDD A and B; its function is the same 12t as that of the STEP pin . JOYSTICK MODE: V for joystick W83877F FUNCTION Publication Release Date: January 1996 Revision A2 ...
Page 12
... Extension Adapter address register, XRD and XWR go low simultaneously so that the command register on the Extension Adapter can latch the same base address. EXTENSION 2FDD MODE: RWC2 This pin is for Extension FDD A and B; its function is the same 12t as that of the RWC pin. JOYSTICK MODE: V for joystick W83877F FUNCTION ...
Page 13
... EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; this function of this pin is the same as INDEX pin. This pin is pulled high internally. JOYSTICK MODE: JP0 This pin is the paddle 0 input for joystick W83877F FUNCTION Publication Release Date: January 1996 Revision A2 ...
Page 14
... EXTENSION ADAPTER MODE: XD2 This pin is system data bus D2 for the Extension Adapter. EXTENSION. 2FDD MODE: WP2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WP pin. This pin is pulled high internally. JOYSTICK MODE: NC pin - 14 - W83877F ...
Page 15
... This pin is a tri-state output. EXTENSION ADAPTER MODE: XD5 This pin is system data bus D5 for the Extension Adapter EXTENSION 2FDD MODE: This pin is a tri-state output. JOYSTICK MODE: JB1 This pin is the button 1 input for the joystick. Publication Release Date: January 1996 - 15 - W83877F Revision A2 ...
Page 16
... EXTENSION FDD MODE: This pin is a tri-state output. EXTENSION ADAPTER MODE: XD7 This pin is system data bus D7 for the Extension Adapter. EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as that of the DSA pin. JOYSTICK MODE: NC pin - 16 - W83877F ...
Page 17
... This schmitt input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN W83877F FUNCTION Publication Release Date: January 1996 Revision A2 ...
Page 18
... FDC FUNCTIONAL DESCRIPTION 2.1 W83877F FDC The floppy disk controller of the W83877F integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports bits/sec data rate ...
Page 19
... FDC based only on DACK . This mode is only available when the FDC has been configured (1/DATA/RATE 1 DELAY MAXIMUM DELAY TO SERVICING AT 500K BPS Data Rate 238.5 S MAXIMUM DELAY TO SERVICING AT 1M BPS Data Rate 118.5 S Publication Release Date: January 1996 - 19 - W83877F Revision A2 ...
Page 20
... FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. 2.1.6 FDC Core The W83877F FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor ...
Page 21
... The number of data bytes written in a sector NCN: New Cylinder Number ND: Non-DMA Mode OW: Overwritten PCN: Present Cylinder Number POLL: Polling Disable PRETRK: Precompensation Start Track Number R: Record RCN: Relative Cylinder Number R/W: Read/Write SC: Sector/per cylinder SK: Skip deleted data address mark Publication Release Date: January 1996 - 21 - W83877F Revision A2 ...
Page 22
... GPL ----------------------- W -------------------- DTL ----------------------- Execution Result R -------------------- ST0 ----------------------- R -------------------- ST1 ----------------------- R -------------------- ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS DS1 DS0 - 22 - W83877F D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution ...
Page 23
... ST2 ----------------------- R ---------------------- C ------------------------ R ---------------------- H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS DS1 DS0 Publication Release Date: January 1996 - 23 - W83877F REMARKS Command codes Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Revision A2 ...
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... H ------------------------ R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS DS1 DS0 - 24 - W83877F D0 REMARKS 0 Command codes Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after command execution Sector ID information after command execution ...
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... HDS DS1 DS0 HDS DS1 DS0 - 25 - W83877F D0 REMARKS 0 Command codes The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D0 REMARKS 0 Command codes Sector ID information prior to command execution No data transfer takes ...
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... HDS DS1 DS0 MFM HDS DS1 DS0 - 26 - W83877F D0 REMARKS 0 Command code 0 Enhanced controller D0 REMARKS 1 Command codes Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution Sector ID information after Command execution D0 REMARKS 1 Command codes ...
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... MFM HDS DS1 DS0 - 27 - W83877F D0 REMARKS Data transfer between the FDD and system Status information after command execution Sector ID information after command execution D0 REMARKS 1 Command codes Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution Publication Release Date: January 1996 ...
Page 28
... DS1 DS0 HDS DS1 DS0 W83877F D0 REMARKS 1 Command codes Head retracted to Track 0 Interrupt D0 REMARKS 0 Command code Status information at the end of each seek operation D0 REMARKS 1 Command codes D0 REMARKS 1 Command codes Head positioned over proper cylinder on diskette D0 REMARKS 1 Configure information 0 Internal registers written ...
Page 29
... ST3 ------------------------- DIR HDS DS1 DS0 GAP GAP LOCK HDS DS1 DS0 - 29 - W83877F D0 REMARKS 1 Command codes D0 REMARKS 0 Registers placed in FIFO D0 REMARKS 0 Command Code D0 REMARKS 0 0 Command Code REMARKS 0 Command Code Status information about disk drive Publication Release Date: January 1996 Revision A2 ...
Page 30
... PHASE R/W D7 Command W ------------- Invalid Codes ----------------- Result R -------------------- ST0 ---------------------- 2.2 Register Descriptions There are several status, data, and control registers in W83877F. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes ...
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... INIT PENDING (Bit 7): This bit indicates the value of the floppy disk interrupt output. DRQ (Bit 6): This bit indicates the value of DRQ output pin. STEP F/F (Bit 5 DIR WP INDEX HEAD TRAK0 STEP F/F INIT PENDING Publication Release Date: January 1996 - 31 - W83877F DRQ Revision A2 ...
Page 32
... This bit indicates the status of DO REGISTER bit 0 (drive select bit 0). WDATA Toggle (Bit 4): This bit changes state at every rising edge of the WD output pin. RDATA Toggle (Bit 3): This bit changes state at every rising edge of the RDATA output pin W83877F MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 ...
Page 33
... This bit indicates the complement of the latched RDATA output pin . WE F/F (Bit 2): This bit indicates the complement of latched WE output pin. DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected W83877F DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 Publication Release Date: January 1996 Revision A2 ...
Page 34
... Motor Enable C. Motor C on when active high Motor Enable D. Motor D on when active high W83877F 01 select drive B 10 select drive C 11 select drive D Tape sel 0 Tape sel 1 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 ...
Page 35
... Transition to LOW state indicates execution phase has ended. DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor W83877F None ...
Page 36
... FDC in normal mode 1 FDC in power-down mode PRECOMP2 PRECOMP1 PRECOMP0 (Bit 4, 3, 2): These three bits select the value of write precompensation. The following tables show the precompensation values for the combination of these bits DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET - 36 - W83877F ...
Page 37
... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83877F, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
Page 38
... OR (Over Rum the FDC is not serviced by the host system within a certain time interval during data transfer. DE (data Error).1 When the FDC detects a CRC error in either the ID field or the data field. Not used. This bit is always 0. EN (End of track). 1 When the FDC tries to access a sector beyond the final sector of a cylinder W83877F ...
Page 39
... Not used. This bit is always Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG - 39 - W83877F US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Publication Release Date: January 1996 Revision A2 ...
Page 40
... DSKCHG (Bit 7): This bit indicates the status of DSKCHG input. Bit 6-4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2 W83877F HIGH DENS DRATE0 DRATE1 DSKCHG 0 DRATE0 DRATE1 NOPREC DMAEN DSKCHG ...
Page 41
... Bit 7-3: Reserved. These bits should be set to 0. NOPREC (Bit 2): This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved - 41 - W83877F 0 DRATE0 DRATE1 0 DRATE0 DRATE1 NOPREC Publication Release Date: January 1996 Revision A2 ...
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... Register Address REGISTERS READ Data Register Data Register Error Register Write-Precomp Sector Count Sector Count Sector Number Sector Number Cylinder LOW Cylinder LOW Cylinder HIGH Cylinder HIGH SDH Register SDH Register Status Register Command Register Alternate Status Fixed Disk Control - 42 - W83877F WRITE ...
Page 43
... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83877F Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt Enable (EHSRI) Interrupt ...
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... TABLE 4-2 WORD LENGTH DEFINITION Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB W83877F ...
Page 45
... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI W83877F Publication Release Date: January 1996 Revision A2 ...
Page 46
... Bit 1: This bit controls the RTS output. The value of this bit is inverted and output to RTS . Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS, Loopback RI input ( bit 2 of HCR) DCD . - 46 - W83877F ...
Page 47
... This register is used to control the FIFO functions of the UART CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD W83877F Publication Release Date: January 1996 Revision A2 ...
Page 48
... Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB W83877F ...
Page 49
... Data present in RX FIFO for 4 characters period of time since last access of RX FIFO. TBR Empty TBR empty Handshake status 1. TCTS = 1 3. FERI = W83877F 0 if interrupt pending Interrupt Status bit 0 Interrupt Status bit 1 Interrupt Status bit 2 FIFOs enabled FIFOs enabled Clear Interrupt - Read USR 1 ...
Page 50
... User-defined Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI W83877F 16 -1. The output frequency of ...
Page 51
... The percentage error for all baud rates, except where indicated otherwise, is 0.16%. Decimal divisor used to Percent error difference between generate 16X clock 2304 1536 1047 857 768 384 192 104* 52* 26* 1* Publication Release Date: January 1996 - 51 - W83877F desired and actual ** ** 0.18% 0.099 0.53 Revision A2 ...
Page 52
... PARALLEL PORT 5.1 Printer Interface Logic The parallel port of the W83877F makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83877F supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), Extension 2FDD mode (EXT2FDD), Extension Adapter mode (EXTADP), and JOYSTICK mode on the parallel port ...
Page 53
... I/O PD6 I/O I/O PD7 I/O I nACK I I BUSY SLCT O O nAFD O I nERR O O nINIT O O nSLIN W83877F EXT2FDD PIN EXTFDD ATTRIBUTE --- DSA2 OD DSB2 DSB2 OD MOB2 MOB2 OD WD2 WD2 OD WE2 WE2 OD RWC2 RWC2 OD NERR2 NERR2 OD DIR2 DIR2 OD STEP2 STEP2 EXTADP ...
Page 54
... Data port (R/W) 1 Printer status buffer (Read) 0 Printer control latch (Write) 0 Printer control swapper (Read) 1 EPP address port (R/W) 0 EPP data port 0 (R/W) 1 EPP data port 1 (R/W) 0 EPP data port 2 (R/W) 1 EPP data port 2 (R/ W83877F NOTE TMOUT ERROR SLCT PE ACK BUSY ...
Page 55
... Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse. 5.2.4 EPP Address Port The address port is available only in EPP mode. Bit definitions are as follows STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR - 55 - W83877F Publication Release Date: January 1996 Revision A2 ...
Page 56
... During a read operation, ports PD0-PD7 are read, and the leading edge of IOR causes an EPP read cycle to be performed and the data to be output to the host CPU auses an EPP address write cycle to be performed, and the W83877F 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 ...
Page 57
... IRQEN 1 1 DIR IRQ PD6 PD5 PD4 PD6 PD5 PD4 PD6 PD5 PD4 PD6 PD5 PD4 PD6 PD5 PD4 EPP DESCRIPTION - 57 - W83877F PD3 PD2 PD1 1 1 TMOUT ERROR SLIN INIT AUTOFD STROBE SLIN INIT AUTOFD STROBE PD3 PD2 PD1 PD3 PD2 ...
Page 58
... Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. Hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard W83877F ...
Page 59
... Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: January 1996 - 59 - W83877F FUNCTION Revision A2 ...
Page 60
... Bit 4: This bit reflects the Select input. Bit 3: This bit reflects the nFault input. Bit 2-0: These three bits are not implemented and are always logic one during a read W83877F 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE Address/RLE 1 nFault Select PError nAck nBusy ...
Page 61
... When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a hardware handshake to the peripheral using the ECP parallel port protocol. Transfers to the FIFO are byte aligned W83877F strobe autofd nInit SelectIn ackIntEn Direction Publication Release Date: January 1996 Revision A2 ...
Page 62
... IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written 5.3.11 ecr (Extended Control Register) Mode = all IRQ resource - 62 - W83877F IRQx 0 IRQx 1 IRQx 2 intrValue compress . ...
Page 63
... Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from W83877F empty full service Intr dmaEn nErrIntrEn MODE MODE MODE Publication Release Date: January 1996 Revision A2 ...
Page 64
... MODE Notes: 1. These registers are available in all modes. 2. All FIFOs use one common 16-byte FIFO. 5.3.12 ECP Pin Descriptions PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr - 64 - W83877F NOTE PD2 PD1 PD0 nInit autofd strobe full empty ...
Page 65
... ECP Mode. O This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. O This signal is always deasserted in ECP mode W83877F DESCRIPTION Publication Release Date: January 1996 Revision A2 ...
Page 66
... PeriphAck is low. The most significant bit of the command is always zero. Data Compression The W83877F supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
Page 67
... Extension Adapter Mode (EXTADP) In this mode, the W83877F redefines the printer interface pins for use as an extension adapter, allowing a pocket peripheral adapter card to be installed through the DB-25 printer connector. The pin assignments for the extension adapter are shown in table 5-1 ...
Page 68
... The operation of EXTADP mode is described below: 1. Set the W83877F to EXTADP mode by programming bit 7 of CR7 as low and bit 3 and bit 2 of CR0 as high and low, respectively. 2. The W83877F CR2 is an address register that records the address of the extension adapter. When the desired address is written into CR2, pins XWR and XRD of the W83877F will simultaneously go low and the desired address will also appear on the printer data bus PD7-PD0 ...
Page 69
... Winbond I/O devices (i.e., the FDC, PRT, UART, IDE, and game port) in the PC's I/O space (100H - 3FFH). In addition, the W83877F also provides 8 interrupt requests and 3 DMA pairs for designers to assign in interfacing FDCs, UARTs, and PRTs. Hence this powerful I/O chip offers greater flexibility for system designers ...
Page 70
... MR = 1). A warm reset will not affect the configuration registers. 8.1 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83877F enters the default operating mode. Before the W83877F enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed ...
Page 71
... Immediate power-down (IPD) state, OSCS2 = 0 When bit and bit 1 is set to 0, the W83877F will stop its oscillator and enter power-down mode immediately. The W83877F will not leave the power-down mode until either a system power-on reset from the MR pin or these two bits are used to program the chip back to power-on state. After leaving the power-down mode, the W83877F must wait 128 mS for the oscillator to stabilize ...
Page 72
... Standby for automatic power-down (APD), OSCS2 = 0 When bit 1 is set to 1 and bit 0 is set to 0, the W83877F will stand by for automatic power-down. A power-down will occur when the following conditions obtain: FDC not busy FDD motor off Interrupt source of line status, modem status, and data ready is inactive (neglecting IER ...
Page 73
... XD1-XD7. After the base address is latched into CR2, a subsequent read/write cycle to this same base address will generate an XRD or XWR signal. If CEA is set to 0, then the W83877F will compare system addresses SA9-SA3 with EA9-EA3 to generate a compare-equal signal for this read/write command to access the Extension adapter. If CEA is set to 1, then only EA9-EA4 are used in this comparison ...
Page 74
... Note: GMDRQ (CR16 bit 3) has higher precedence over this bit. That is, GMODS selection is only valid when GMGRQ = 0. EPPVER (Bit 5): This bit selects the EPP version of parallel port: 0 Selects the EPP 1.9 version 1 Selects the EPP 1.7 version (default) Bit 7-bit 6: Reserved W83877F SUBMIDI SUAMIDI reserved reserved GMODS EPPVER GMENL reserved ...
Page 75
... The output pins of the game port will not be tri-stated when game port is in power- down mode. (default) 1 The output pins of the game port will be tri-stated when game port is in power-down mode. URATRI (Bit 1 W83877F URBTRI URATRI GMTRI PRTTRI URBPWD URAPWD GMPWD PRTPWD Publication Release Date: January 1996 Revision A2 ...
Page 76
... Configuration Register 6 (CR6), default = 00H When the device is in Extended Function mode and EFIR is 06H, the CR6 register can be accessed through EFDR. The bit definitions are as follows W83877F ECPFTHR0 ECPFTHR1 ECPFTHR2 ECPFTHR3 Reserved Reserved Reserved Reserved IDETRI FDCTRI IDEPWD FDCPWD FIPURDWM SEL4FDD OSCS2 Reserved ...
Page 77
... Bit 7: Reserved OSCS2 (Bit 6): This bit and OSCS1, OSCS0 (bit CR0) select one of the W83877F's power-down functions. Refer to descriptions of CR0. (Default SEL4FDD (Bit 5): Selects four FDD mode 0 Selects two FDD mode (default, see Table 7-2) 1 Selects four FDD mode DSA , DSB , MOA and MOB output pins are encoded as show in Table 7-3 to select four drives ...
Page 78
... Three mode FDD select (EN3MODE = 1): 01 RWC = 0, selects 1.2 MB high-density FDD. 10 RWC = 1, selects 1.44 MB high-density FDD. 11 Don't care RWC FDD B type 1, 0 (Bit 3, 2 selects 720 KB double-density FDD W83877F FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type 1 ...
Page 79
... When the device is in Extended Function mode and EFIR is 08H, the CR8 register can be accessed through EFDR. The bit definitions are as follows Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1 SWWP DISFDDWR APDTMS2 APDTMS1 - 79 - W83877F Publication Release Date: January 1996 Revision A2 ...
Page 80
... Media ID 1 Media ID 0 (Bit 3, 2): These two bits hold the media ID bit 1, 0 for three mode Floppy Boot Drive 1 Floppy Boot Drive 0 (bit 1, 0) These two bits hold the value of floppy boot drive 1 and drive 0 for three mode 8.2.10 Configuration Register 9 (CR9), default = 0AH - 80 - W83877F ...
Page 81
... This bit enables or disables the reading and writing of all configuration registers. 0 Enables the reading and writing of CR0-CR29 1 Disables the reading and writing of CR0-CR29 (locks W83877F extension functions) EN3MODE (Bit 5): This bit enables or disables three mode FDD selection. When this bit is high, it enables the read/write 3F3H register. ...
Page 82
... This bit controls whether the PEXTEN pin is active in EXTADP mode. 0 PEXTEN is not active in EXTADP mode 1 PEXTEN is active in EXTADP mode PEXTEPP (Bit 2): This bit controls whether the PEXTEN pin is active in EPP mode. 0 PEXTEN is not active in EPP mode W83877F PEXTECPP PEXT ECP PEXT EPP PEXT ADP PDCACT PDIRHOP PEXT ACT PFDCACT ...
Page 83
... RWC will be active high for high data rates (typically used for 5.25" drives) When hardware reset or ENIFCHG is a logic 1, IDENT and MFM select one of three interface modes, as shown in Table 7-5. Table 7- 5 IDENT MFM INTERFACE - 83 - W83877F DRV2EN INVERTZ MFM IDENT ENIFCHG Publication Release Date: January 1996 Revision A2 ...
Page 84
... MHz TURB (bit 6): 0 the clock source of UART B is 1.8462 MHz (24 MHz divide 13) (default) 1 the clock source of UART MHz, it can make the baudrate of UART 1.5 MHz Model 30 mode PS/2 mode AT mode AT mode W83877F TX2INV RX2INV Reserved URIRSEL Reserved HEFERE TURB TURA ...
Page 85
... W83877F IRMODE0 IRMODE1 IRMODE2 HDUPLX SIRRX0 SIRRX1 SIRTX0 SIRTX1 Publication Release Date: January 1996 Revision A2 ...
Page 86
... Active pulse 1.6 S Active pulse 3/16 bit time Inverting IRTX pin Inverting IRTX & 500 KHZ clock Inverting IRTX Inverting IRTX & 500 KHZ clock - 86 - W83877F IRRX high Demodulation into SINB Demodulation into SINB routed to SINB routed to SINB Demodulation into SINB ...
Page 87
... IRMODE1 (CRD.bit2) (CRD.bit1) 1 IRDA 0 0 MUX 0 1 MUX IRMODE0 1 MUX (CRD.bit0) IRMODE2 (CRD.bit2) 1 URIRSEL (CRC,bit3) 0 MUX IRMODE0 (CRD.bit0 W83877F IRRX1 SIN2 01 00 +5V IRRX2 NCS0 (default) 10 MUX +5V 11 SIRRX1~0 CR0D.bit5,4 disable 11,00 IRTX1 SOUT2 01 IRTX2 NCS1 (default) 10 MUX TX2INV CRC.bit0 SIRTX1~0 CRD.bit7,6 ...
Page 88
... G0CADM1-G0CADM0 (bit 7-bit 6): GIOP0 address bit compare mode selection G0CADM1 G0CADM0 Bit 5-bit 3: Reserved GIO0AD10-GIO0AD8 (bit 2-bit 0): GIOP0 (pin 92) address bit 10-bit GIOP0 pin compare GIO0AD10-GIO0AD0 with SA10-SA0 compare GIO0AD10-GIO0AD1 with SA10-SA1 compare GIO0AD10-GIO0AD2 with SA10-SA2 compare GIO0AD10-GIO0AD3 with SA10-SA3 - 88 - W83877F 0 GIO0AD8 GIO0AD9 GIO0AD10 Reserved Reserved Reserved G0CADM0 G0CADM1 ...
Page 89
... GIO1AD8 GIO1AD9 GIO1AD10 Reserved Reserved Reserved G1CADM0 G1CADM1 GIOP1 pin compare GIO1AD10-GIO1AD0 with SA10-SA0 compare GIO1AD10-GIO1AD1 with SA10-SA1 compare GIO1AD10-GIO1AD2 with SA10-SA2 compare GIO1AD10-GIO1AD3 with SA10-SA3 Publication Release Date: January 1996 - 89 - W83877F GIO1AD0 GIO1AD1 GIO1AD2 GIO1AD3 GIO1AD4 GIO1AD5 GIO1AD6 GIO1AD7 Revision A2 ...
Page 90
... GIO0AD10-0), the value of SD0 will be present on GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10 GIO0AD10-0), the value of GIOP0 will be present on SD0 Chip Select pin, the pin will be active at (AEN = L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR (NIOW = W83877F 0 GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 ...
Page 91
... Configuration Register 15 (CR15), default = 00H When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed through EFDR. The bit definitions are as follows W83877F GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2 Publication Release Date: January 1996 Revision A2 ...
Page 92
... L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L) GIOP1 functions as a Chip Select pin, and will be active when (AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOR = L) GIOP1 functions as a Chip Select pin, and will be active when (AEN = L) AND (SA10-0 = GIO1AD10-0) AND (NIOW = L OR NIOR = W83877F GIOP1 pin ...
Page 93
... GIOP1 functions as a data pin, and inverse GIOP1 SD1, SD1 GIOP1 GIOP1 functions as a data pin, and GIOP1 SD1, inverse SD1 GIOP1 GIOP1 functions as a data pin, and inverse GIOP1 SD1 GIOP1 W83877F SD1, inverse 0 HEFRAS IRIDE PNPCVS GMDRQ GOIQSEL Reserved Reserved Reserved Publication Release Date: January 1996 Revision A2 ...
Page 94
... When the device is in Extended Function mode and EFIR is 17H, the CR17 register can be accessed through EFDR. The bit definitions are as follows: PNPCVS = 0 81H 00H FCH 00H 7CH 00H FDH 00H DEH 00H FEH 00H BEH 00H 23H 00H 65H 00H 43H 00H 62H 00H IRIDE = 1 IRQ_G IRQ_H IRRX2 IRTX2 - 94 - W83877F ...
Page 95
... DSUBLGRQ (bit 0): 0 enable UART B legacy mode on IRQ selection. MCR bit 3 has effect on selecting IRQ. 1 disable UART B legacy mode on IRQ selection. MCR bit 3 has no effect on selecting IRQ W83877F DSUBLGRQ DSUALGRQ DSPRLGRQ DSFDLGRQ PRIRQOD Reserved Reserved Reserved Publication Release Date: January 1996 Revision A2 ...
Page 96
... NCS = 0 and A10 = 0 are required to access the FDC registers. A[3:0] are always decoded as 0xxxb. FDCAD7-FDCAD2 (bit 7-bit 2): match A[9:4]. Bit and bit disable this decode. Bit 1-bit 0: Reserved, fixed at zero. 8.2.26 Configuration Register 21 (CR21 W83877F 0 GMAS0 GMAS1 GMAD2 GMAD3 GMAD4 GMAD5 GMAD6 GMAD7 0 Reserved Reserved FDCAD2 FDCAD3 FDCAD4 FDCAD5 FDCAD6 ...
Page 97
... Alternate Status register. A[3:0] must be 0110b. IDE1AD7-IDE1AD2 (bit 7-bit 2): match A[9:4]. Bit and bit disable this decode. Bit 1: Reserved, fixed at zero. Bit 0: Reserved, fixed at one. 8.2.28 Configuration Register 23 (CR23 W83877F 0 Reserved Reserved IDE0AD2 IDE0AD3 IDE0AD4 IDE0AD5 IDE0AD6 IDE0AD7 0 Reserved Reserved IDE1AD2 IDE1AD3 IDE1AD4 IDE1AD5 ...
Page 98
... NCS = 0 and A10 = 0 are required to access the UART A registers. A[2:0] are don't-care conditions. URAAD7-URAAD1 (bit 7-bit 1): match A[9:3]. Bit and bit disable this decode. Bit 0: Reserved, fixed at zero W83877F 0 PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 PRTAD5 PRTAD6 PRTAD7 0 Reserved URAAD1 URAAD2 URAAD3 URAAD4 URAAD5 ...
Page 99
... PRTDQS3-PRTDQS0 (bit 3-bit 0): Allocate DMA resource for PRT. bit 7- bit4, bit 3 - bit 0 0000 0001 0010 0011 DMA selected None DMA_A DMA_B DMA_C - 99 - W83877F 0 Reserved URBAD1 URBAD2 URBAD3 URBAD4 URBAD5 URBAD6 URBAD7 0 PRTDQS0 PRTDQS1 PRTDQS2 PRTDQS3 FDCDQS0 FDCDQS1 FDCDQS2 FDCDQS3 Publication Release Date: January 1996 Revision A2 ...
Page 100
... PRTIQS3-PRTIQS0 (bit 3-bit 0): Select IRQ resource for the parallel port. Any unselected IRQ is in tristate. CR27[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 IRQ resource IRQ selected None IRQ_A IRQ_B IRQ_C IRQ_D IRQ_E IRQ_F IRQ_G IRQ_H - 100 - W83877F 0 PRTIQS0 PRTIQS1 PRTIQS2 PRTIQS3 Reserved ECPIRQx0 ECPIRQx1 ECPIRQx2 ...
Page 101
... EFDR. Default = 62H if CR6 bit default = 00H if CR16 bit The bit definitions are as follows: 7 FDCIQS3-FDCIQS0 (bit 7-bit 4): Allocate interrupt resource for FDC. IQNIQS3-IQNIQS0 (bit 3-bit 0): Allocate interrupt resource for IRQIN 101 - W83877F 0 URBIQS0 URBIQS1 URBIQS2 URBIQS3 URAIQS0 URAIQS1 URAIQS2 URAIQS3 0 IQNIQS0 IQNIQS1 IQNIQS2 IQNIQS3 FDCIQS0 FDCIQS1 FDCIQS2 ...
Page 102
... IDE1AD5 IDE1AD4 PRTAD6 PRTAD5 PRTAD4 URAAD6 URAAD5 URAAD4 URBAD6 URBAD5 URBAD4 FDCDQS2 FDCDQS1 FDCDQS0 ECPIRQx1 ECPIRQx0 0 URAIQS2 URAIQS1 URAIQS0 FDCIQS2 FDCIQS1 FDCIQS0 - 102 - W83877F PRTMODS1 PRTMODS0 OSCS1 RA5 RA4 RA3 0 0 SUAMIDI PRTTRI GMTRI URATRI ECPFTHR1 ECPFTHR3 ECPFTHR2 FDCPWD IDEPWD FDCTRI ...
Page 103
... +70 -55 to+ 150 = 0V) SS MIN. MAX. V -0.5 0 2 0 +10 LIH I -10 LIL V -0.5 0 2 0 +10 LIH I -10 LIL V -0.5 0 2 0 103 - W83877F UNIT V +0 UNIT CONDITIONS - - Publication Release Date: January 1996 Revision A2 ...
Page 104
... Input Low Voltage V Input High Voltage V Input High Leakage I LIH Input Low Leakage I MIN. MAX. +10 -10 LIL 0.4 OL 2.4 OH 0.4 OL 2.4 OH 0.4 OL 0.4 OL -0.5 0.8 IL 2 +10 -10 LIL -0.5 0 +0.5 0 +10 -10 LIL -0.5 1.8 IL 3 +10 -10 LIL - 104 - W83877F UNIT CONDITIONS - ...
Page 105
... DRQ delay time DACK ¡õ DRQ to DACK delay DACK width IOR delay from DRQ IOW delay from DRQ SYM. TEST MIN. CONDITIONS 100 100 100 MCY 260/430 AA /510 105 - W83877F TYP. MAX. (NOTE 360/570 /675 0 0 360/570 /675 Publication Release Date: January 1996 Revision A2 UNIT ...
Page 106
... TC T 1.8/3/3. RST T 0.5/0.9 IDX T 1.0/1.6 DST T 24/40/48 STD T 6.8/11.5 STP T Note 100/185 WDD T 100/138 WPC - 106 - W83877F MIN. TYP. MAX. (NOTE 1) 6/12 /20/24 /260 5 /1.0 /2.0 7/11.7 7.2/11.9 /13.8 /14 /14.2 Note 2 Note 2 125/210 150/235 /225 /250 /275 125/210 150/235 /225 ...
Page 107
... Loading IID N 100 pF Loading SYM. TEST MIN. CONDITIONS tx1 tx2 tx3 50 tx4 0 tx5 tx6 tx7 tx8 Publication Release Date: January 1996 - 107 - W83877F MIN. MAX. UNIT 9/16 Baud Rate 1 S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 ...
Page 108
... Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command SYM. MIN. TYP 200 t5 SYM. MIN t10 0 t13 0 t14 0 t15 60 t16 0 t17 60 t18 0 t19 0 t20 60 t21 1 - 108 - W83877F MAX. UNIT 100 105 nS 300 nS 105 nS MAX. UNIT 160 185 nS 190 180 190 nS nS ...
Page 109
... Command Asserted to WAIT Deasserted SYM. MIN. t22 0 t23 0 t24 0 t25 60 t26 10 t27 0 t28 0 SYM. MIN t10 0 t11 60 t12 60 t13 0 t14 0 t15 10 t16 5 t17 60 t18 60 t19 0 Publication Release Date: January 1996 - 109 - W83877F MAX. UNIT 195 nS 180 MAX. UNIT 160 185 nS 185 210 nS 190 Revision A2 ...
Page 110
... Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted 10.0 TIMING WAVEFORMS SYM. MIN. t20 10 t21 0 t22 0 SYMBOL MIN. t1 600 t2 600 t3 450 680 t6 SYMBOL MIN SYMBOL MIN 110 - W83877F MAX. UNIT MAX. UNIT 500 nS MAX. UNIT 180 nS 180 nS nS 200 nS nS 180 nS MAX. UNIT 200 nS 200 nS ...
Page 111
... IOW or IOR TMW (IOW) TMR (IOR) TRA TRR TDH TDF TR TWA TWW TWD TDW TWI DIR TMCY TAA STEP - 111 - W83877F Write Date WD TWDD Index INDEX TIDX TIDX Terminal Count TC TTC Reset RESET TRST Drive Seek operation TSTP TDST TSTD TSC ...
Page 112
... IDE SA<0:9> IOR IOW DATA READ IDED7 D7 DATA WRITE IDED7 D7 CS0 CS1 IOCS16 DBENL DBENH 112 - W83877F ...
Page 113
... THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) PARITY Transmitter Timing STAR DATA (5-8) PARITY THR TSI - 113 - W83877F STOP TSINT TRINT STAR STOP (1-2) TSTI TIR Publication Release Date: January 1996 Revision A2 ...
Page 114
... Printer Interrupt Timing ¢x ¢x ¢x ¢ ¢x ¡÷ ¡ö ¢x TLAD ¢x ¢x ¢x ¢x ¢ ¢x ¢x - 114 - W83877F ¢x ¢x ¢x ¡÷ ¡ö TMWO ¢x ¢ ¢x ¢x ¢x ¢x ¢ ¡ö TSIM ¢x ¢x ¢ ...
Page 115
... Parallel Port 10.4.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication Release Date: January 1996 - 115 - W83877F Revision A2 ...
Page 116
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT t18 t17 t21 t25 t27 t26 - 116 - W83877F t15 t19 t20 t28 ...
Page 117
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t10 t11 t13 t15 t16 t17 t18 t19 t20 - 117 - W83877F t12 t14 t21 Publication Release Date: January 1996 Revision A2 ...
Page 118
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t22 t23 ADDRSTB t24 DATASTB WAIT t18 t21 t25 t26 t27 - 118 - W83877F t15 t19 t20 t28 ...
Page 119
... A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 10.4.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 >| t6 >| - 119 - W83877F t22 t22 t4 >| t3 >| t5 > >| Publication Release Date: January 1996 Revision A2 ...
Page 120
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 10.4.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD 120 - W83877F ...
Page 121
... Extension Adapter Mode Command Cycle IOR IOW XRD XWR tx1 SA<0:2> XA<0:2> tx2 XD<0:7> 10.4.10 Extension Adapter Mode Interrupt Cycle XIRQ IRQ7 tx3 tx5 Publication Release Date: January 1996 - 121 - W83877F tx4 Revision A2 ...
Page 122
... RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram tx6 tx7 tx8 JP13 - 122 - W83877F JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 ...
Page 123
... DCH2/PD4 18 RDD2/PD3 5 STEP2/SLIN 17 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension 2FDD Connection Diagram JP13 - 123 - W83877F JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 20 19 DIR2 ...
Page 124
... Four FDD Mode W83777F DSA DSB MOA MOB Signal 81K 81K Joystick 15-pin connector 74LS139 7407(2) G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 124 - W83877F Joystick Printer Port 15-pin 25-pin Connector Connector VDD 1,8,9,15 1,14,15,16,17 GND 4,5,12 18~ DSA DSB DSC DSD MOA ...
Page 125
... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27516023 FAX: 852-27552064 - 125 - W83877F Dimension in inches Dimension in mm Symbol Min. Nom. Max. Nom. Min. Max. A 0.130 3.30 A 0.004 0. 0.107 0.112 0.117 2 ...