HEF4751VD Philips Semiconductors, HEF4751VD Datasheet
HEF4751VD
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HEF4751VD Summary of contents
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DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4751V LSI Universal divider Product specification File under Integrated Circuits, IC04 INTEGRATED ...
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... H stage ( stage for half channel offset). Programming is performed in BCD code in a bit-parallel, digit-serial format. HEF4751VP(N): 28-lead DIL; plastic (SOT117) HEF4751VD(F): 28-lead DIL; ceramic (cerdip) (SOT135V) HEF4751VT(D): 28-lead SO; plastic (SOT136A Package Designator North America SUPPLY VOLTAGE RATING ...
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... Philips Semiconductors Universal divider January 1995 Fig.2 Block diagram. 3 Product specification HEF4751V LSI ...
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... Philips Semiconductors Universal divider Fig.4 Timing diagram showing programme data inputs. Allocation of data input INPUTS FETCH PERIOD January 1995 Allocation of data input during fetch period channel X L control control H H Notes HIGH state (the more positive voltage LOW state (the less positive voltage) 3 ...
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... Philips Semiconductors Universal divider PROGRAMME DATA INPUT (see also Figs 3 and 4) The programming process is timed and controlled by input PC and PE. When the programme enable (PE) input is HIGH; the positive edges of the programme clock (PC) signal step through the internal programme counter in a sequence of 8 states. Seven states define fetch periods, ...
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... Philips Semiconductors Universal divider Fig.6 Timing diagram showing signals occurring in Fig.5. January 1995 Fig.5 Block diagram showing feedback to prescalers. 7 Product specification HEF4751V LSI ...
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... Philips Semiconductors Universal divider CASCADING OF U.D.s (see also Fig U.D. is programmed into the ‘slave’ mode by the programme input data 11 U.D. operating in the slave mode performs the function of two extra programmable stages C2’ and C3’ ‘master’ (not slave) mode operating U.D. More slave U.D.s may be used, every slave adding two lower significant digits to the system ...
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Acrobat reader. white to force landscape pages to be ... Fig.8 Block diagram showing cascading of U.Ds. ...
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... Philips Semiconductors Universal divider DC CHARACTERISTICS Output (sink) 4,75 current LOW 5 10 Output (source) 5 current HIGH CHARACTERISTICS input transition times SS amb V DD PARAMETER V Propagation delay 5 IN OSY 10 HIGH to LOW Output transition times HIGH to LOW 5 10 LOW to HIGH 5 10 Maximum input 5 frequency Maximum input 5 frequency ...