W9960CF Winbond, W9960CF Datasheet
W9960CF
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W9960CF Summary of contents
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... VIDEO CODEC Technical Reference Manual Winbond Confidential W9960CF Version 1.11 June, 1997 June 1997 ...
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... Winbond assumes no responsibility or liability arising from the specification listed herein. Winbond makes no representations that the use of its products in the manner described in this publication will not infringe on existing or future patent, trademark, copyright, or rights of third parties ...
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... ROGRAMMABLE NPUT 3. ARIABLE ENGTH ODE 3. UDIO OPROCESSOR NTERFACE 3. ARIABLE ENGTH ODE 3.19 ISA- I .............................................................................................. 49 LIKE NTERFACE 4. W9960CF REGISTERS .......................................................................................... 51 4.1 PCI C R ONFIGURATION EGISTERS 5. ELECTRICAL SPECIFICATIONS....................................................................... 57 5 BSOLUTE AXIMUM ATINGS Winbond Confidential ( FDMA )...................................................... 20 ( XDMA )................................................ 26 ONTROLLER ................................................................................... 28 ................................................................... 30 ONTROLLER ( XINTC ) ............................................................... ..................................................... 33 NPUT UPUT ORT E ................................................................... 35 NGINE ...
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... AUDIO Interface AC Timing............................................................................. 60 5.3.5 DRAM Interface AC Timing .............................................................................. 61 5.3.6 GPIO AC Timing............................................................................................... 62 5.3.7 Video PreProcessor AC Timing......................................................................... 63 5.3.8 ISA-Like Bus AC Timing ................................................................................... 64 6. APPENDIXES ......................................................................................................... 65 6 W9960 W ORTING UIDE FOR 6 IRMWARE OADING RECEDURE 6 PPLICATION IRMWARE Winbond Confidential ............................................... 65 IN EVICE RIVER ............................................................................ 65 B ............................................................ 65 OMMAND LOCK June 1997 ...
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... W9960CF is composed of a high performance RISC processor core (VRISC), function blocks for video encoding/decoding and a downloadable program memory such that the system can be run- time configured for a variety of video applications. The function blocks in W9960CF are computing engines for: Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform ...
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... Supports PCI master mode to access graphics adapters for video displaying Supports panning and zooming over video input Provides audio connection to external audio DSP modules Uses conventional FPM and EDO DRAM No SRAM required Optimized for 3.3 volts operation 0.5um CMOS technology 208-pin PQFP package Winbond Confidential June 1997 ...
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... I CLK 201 I RST# 200 I Winbond Confidential Function PCI BUS (50 pins) IO Address and Data are multiplexed on the same PCI pins. The address phase is the clock cycle in which FRAME# is asserted. During data phase AD7-AD0 contain the least significant byte (lsb) and AD31-AD24 contain the most ...
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... SCLK 152 VD15-VD0 186-184, 179- 169, 164-163 HS/HRESET# 187 VS/VRESET# 188 HREF/ACTive 189 Dvalid 193 Winbond Confidential Connect to GPIO bus to video decoder or coprocessor Function DRAM BUS (50 pins) IO DRAM Data Bus O DRAM Output Enable O DRAM Row Address Strobes O DRAM Column Address Strobes ...
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... EINT1# 192 EINT2# 208 BTEN# 190 BTFLAG# 191 CLK_MEM 69 CLK_Video 194 Note Input with internal pull-high Pad Winbond Confidential Function ISA-Like BUS ( 30 pins ) IO 8-bit Parallel Data Bus O 16-bit Parallel Address Bus O IO Read Control signal O IO Write Control signal IU External Interrupt #1 ...
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... Type VDD 1,10,24,38,53, 61,76,92,105, 114,128,142, 157,165,180, 195 VSS 3,13,27,41,50, 55,64,79,95, 102, 107,117,131, 145, 154, 159, 168, 183, 198, 206 VDD5V 52,104,156 NC 2,11,12, 39, 40, 51, 146, 147 Winbond Confidential Function POWER ( 39 pins ) 3.3V DC Power supply Ground 5.0V DC Power supply pins ) No Connection June 1997 ...
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... VD12 180 VDDI SAIOR# SAIOW# VSSI VD13 185 VD14 VD15 HRESET# VRESET# ACTive 190 BTEN# BTFLAG# EINT1# Dvalid CLK_Video 195 VDDB SADATA0 SADATA1 VSSB INTA# 200 RST# CLK GNT# REQ# AD31 205 AD30 VSSI SADATA2 EINT2 Winbond Confidential W9960CF Video CODEC ...
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... W9960CF is composed of a high performance RISC processor core (VRISC), function blocks for video encoding/decoding and a downloadable program memory such that the system can be run- time configured for a variety of video applications. The figure is a block diagram for W9960CF. Frame Memory DMA Controller ...
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... W9960CF provides PCI master/slave Interface. In the master mode, it supports fast DMA data transfer for video/audio bitstream, picture direct draw to graphic display device and VRISC firmware download. In the slave mode, there are two Base Address Registers for W9960CF internal registers and external DRAM accessing by the host processor. All data accessing, except for configuration registers, should be word (2-byte) or double word (4-byte) read/write operations ...
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... DM memory accessing, and address 000400H through 1FFFFFH is for external DRAM accessing. VRISC cannot access the external DRAM from address 000000H through 0003FFH since this address space are reserved for internal registers and DM memory. Winbond Confidential Instruction Fetch (IF), RISC Bus ...
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... Program Address Space 11FFH 22bits 000000H Data Memory Address Space (2M) 1FFFFFH 16bit Data Memory Addressing Space Winbond Confidential Booting Interrupt Vector Address Space Program Addressing Space Engine Register Address Space (512 Address Space (512 Address Space 0000H 0001H 001FH 000000H ...
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... VRISC has 32 16-bit general registers to provide the resource for all computation. They are numbered as R0 through R31. R0 delivers zero when referenced as a source operand. When R0 is used as destination, the result is discarded Interrupt Handling Vector Name 0000h 0001h MERDY 0002h FRDY 0003h TendINT Winbond Confidential 15 R#[15: Engine Description main program starting address ME ...
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... DREQ_ENCF 001Eh DREQ_DECF 001Fh DREQ_IPTF Winbond Confidential (D) DCT/IDCT DCT ready interrupt (E) XDMA XDMA TC interrupt Ext. Interrupt External Interrupt VLE VLE ready interrupt TIMER DTR time out interrupt TIMER ETR time out interrupt ...
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... The last instruction of a service routine is the RET instruction, which restores all status from the shadow registers and then the VRISC resumes the original program flow (path4). Winbond Confidential June 1997 ...
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... VRISC Address Name 008H MPZ0 009H PC0 00AH IR0_L 00BH IR0_H 00CH TEMPRES_H 00DH TEMPRES_L Winbond Confidential RISC start Jmp main Jmp Int1 Jmp Int2 path1 Jmp DMAint13 Jmp DMAint14 path2 Jmp DMAint15 N N+1 Int1 Service task ...
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... DRQIDCTR_D DCT/IDCT 6 DRQDCTR_E DCT/IDCT 7 dreqV Video_In 8 dreqU Video_In 9 dreqY Video_In 10 dreqY Video_Out 11 dreqU Video_Out 12 dreqV Video_Out 13 DREQ_ENCF PIO 14 DREQ_DECF PIO 15 DREQ_IPTF PIO Winbond Confidential direction U LIN dmd R/W M> > > > > > > > M dmd R E > M dmd R E > M dmd R M > E ...
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... PCI issues CBR_(CPU Bus Request) to get memory bus when VRISC is working. Also, VRISC can interrupt FDMA by issuing a MBR_(Memory Bus Request) signal to get access to memory bus 3.4.2 FDMA T T RANSFER YPE The FDMA do Unrestricted Mode when the start point of picture is out of picture boundary. Winbond Confidential DACK DH SDMA TCMSK Engine ...
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... Block addressing mode : The following is the relation between DRAM address and Engine address DRAM FMSA = 1000 finit = 1023 1026 1033 1036 1043 1046 1053 1056 1099 Winbond Confidential Video_In Video_Out PICTURE (0,0) (9,0) PSP(3,2) (9,9) (0,9) PH=9 PW=9 DRAM Picture Engine ...
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... Engine start point : ESP = ( Enable DMASK 7. In demand mode, the DMA service will pause if DMA request becomes inactive, and the service will continue if DMA request is active again. 8. FDMA still transfers two sets of data after DMA request becomes inactive in demand mode. Winbond Confidential ...
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... Register of X_axis, Picture Start Point Register of Y_axis and Frame Memory Start Address Register. DRAM FMSA FMSA+[(PW+1)(PH+1)-1] FDMA Registers List RISC Address/PCI Offset Address 0040H - 004FH/0100H - 013CH 0050H - 005FH/ 0140H - 017CH 0060H - 006FH/ 0180H - 01BCH 0070H - 007FH,/ 01C0H - 01FCH Winbond Confidential 0,0 ) Picture PSP DMA Transfer (0,0) ESP Name Read/Write ...
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... RISC Address/PCI Offset Address 0030H/00C0H 0031H/00C4H 0032H/00C8H 0033H/00CCH 0034H/00D0H 0035H/00D4H 0037H/00DCH Winbond Confidential Name Read/Write Description DMA_Index R/W FDMA Index Register DMSK R/W FDMA Mask Register SDMA R/W Software FDMA DSTS R/W FDMA Status Register DTS R TC Status Register TCMSK R/W ...
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... Read XDTS register: while DMA operation has been completed and XDMA issues a TC interrupt to host or VRISC, the interrupt service routine has to read the XDTS register (TC status of XDMA) to clear the TC flag, so that the XDMA can continue with the next DMA operation. Winbond Confidential June 1997 ...
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... RISC Address/PCI Offset Address 0038H/00E0H 0039H/00E4H 003AH/00E8H 003BH/00ECH 003CH/00F0H 003DH/00F4H 003EH/00F8H 003FH/00FCH Winbond Confidential Direction R/W LIN dmd Description E > PCI R * dmd Remote Video out E > PCI R * dmd Local Video out E > PCI R LIN dmd Bit-stream for Audio out PCI > ...
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... DRAM Memory Interface W9960CF provides a 32-bit DRAM data bus for DMA data transfer and VRISC access. It supports the control timing for Fast Page Mode or EDO DRAMs. The DRAM address space has three types of configurations: 1M, 2M, and 4M bytes. For 1M and 2M-byte space, the DRAM devices must be two or four 256Kx16 DRAM devices ...
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... MD[31:0] At E6F4 Mode (EDO-60, 40MHz ) CLK MCS# RAS# CAS# Row Addr. ADD[9:0] R Write to DRAM WE# MD[31:0] mrdy_ edowr_ Read from DRAM OE# MD[31:0] mrdy_ edowr_ Winbond Confidential Column Column Column Column C C+1 C+2 C+3 Data Data Data Data C C+1 C+2 C+3 Data Data ...
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... INTR DTR_INT 9 INTR ETR_INT 10 INTR TOUT0 11 INTR TOUT1 12 INTR PCI_INT 13 INTR VLRDY_INT 14 INTR UFRAME_INT UFRAME_INTA 15 INTR VLDREQ_INT VLDREQ_INTA Winbond Confidential INTG_OUT ENGINE VideoPre METG ME F_TRIGGER FILTER TriggerDEC DCT/IDCT TriggerENC DCT/IDCT XDMA ISA-Like VLETCO TIMER TIMER TIMER TIMER HOST TG_INTA PIO PIO ...
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... Block Diagram Irdy IMSK CPU_Bus INTG Registers RISC Address/PCI Offset Address 0019H/0064H 001AH/0068H 001BH/006CH 001CH/0070H 001DH/0074H Winbond Confidential ISR IVEC Queue INT ITrig TMODE STG Name Read/Write Description IMSK R/W Interrupt Mask Register ISR R Interrupt Status Register IVEC R/W Interrupt Vector Register ...
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... XDMA and FDMA. Channel#15 is the interrupt from INTC controller. All channels are maskable by XMSK register. Host has to read the XSTS register to identify interrupt source when receiving a W9960CF issued interrupt. Host issues interrupt to VRISC by programming PCI_INT register, which will generate a interrupt trigger pulse for VRISC to enter interrupt service routine ...
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... GPIO ( General Purpose Input/Ouput) Port W9960CF provides 4 pins as a GPIO port. These four pins are programmable to be input or output. GPIO0 and GPIO1 are two open drain IO pads and pull-high resistors are necessary in application circuits. GPIO2 and GPIO3 are tri-state IO pads. GPIO port is used to connect to external devices such as analog video decoder and/or audio coprocessor ...
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... Pre-Scaler 16 (/ register 16 TIMER Registers RISC Address / PCI Offset Address 010H / 040H 011H / 044H 012H / 048H 013H / 04CH 014H / 050H 015H / 054H 016H / 058H 017H / 05CH Winbond Confidential Counter Counter (8 stages) (8 stages Comparetor TOUT Interrupt Name Read/Write PSR R/W Pre-Scale Register TR0 R ...
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... PAL 704 288 on on Winbond Confidential VA VD YUV 422 1/2H 1/2H v 420 ScaleH ( 1, 1/2, 1/4 ) Video PreProcess Diagram Scale Scale 1/5 Picture Size off 704 1/2 ...
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... YUV422 or RGB565 video output. VPOST provides FIFO for DMA data transfer. The size of Y FIFO is 16x4bytes. U FIFO and V FIFO is 8x4 bytes each. X_Bus Colour Vout PACK Space Convert YUV422 -> RGB565 Video PostProcessor Diagram Winbond Confidential 1/2 1 off 352 1 1/2 off 352 1/2 ...
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... VIDEO Register RISC Address/PCI Offset Address 01A0H/0680H 01A1H/0684H 01A2H/0688H 01A3H/068CH 01A4H/0690H 015AH/0694H 01A6H/0698H 01A7H/069CH Winbond Confidential Name Read/Write VPRE Mode R/W Video Preprocessing operation mode HDelay R/W Horizontal delay pixel number VDelay R/W Vertical delay line number HA R/W Horizontal active pixel number ...
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... Motion Estimation Engine W9960CF motion estimation (ME) engine implements full search matching algorithm (FSA), which is widely used thanks to its simplicity and regularity. In this algorithm, for each reference block in the current frame, the previous frame is searched within a neighborhood, i.e. search window, to find the most matched pixel block. ...
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... The Filter Engine also performs the interpolation function of half pixel prediction and PB frame prediction in H.263. H.261 8x8 predicted Block with 1-2-1 Filter Winbond Confidential (1) 1/ for pixels inside the block (2) 1/ for pixels on the block edge 47 55 (3) 1/ for pixels on the block corner positions June 1997 ...
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... The prediction picture is transferred into Filter Engine by DMA operation. Half Pixel PreProcessor module performs the half pixel interpolation in x-axial direction. HPP module performs the half pixel interpolation in y-axial direction. OMC module performs PB frame prediction. The control flow is specified in FCR0 (Filter Control Register #0) and BRR (Bi- direction Range Register) registers. Winbond Confidential ...
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... Input from DRAM Controller Half Pixel PreProcessor 8 9 dmablk F/F 0,1/4, 2/4 F/F F/F CSA ADDER HPP F/F Filter Registers RISC Address / PCI Offset Address 018CH / 0630H 018DH / 0634H 018EH / 0638H Winbond Confidential MUX MUX F/F F/F 0,1,2/8,4/8 4/8,8/8,4/8,8/8 0,2/4,4/4 CSA 0,1/4 ADDER OMC ...
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... FIDCT/Q/IQ Engine W9960CF contains Forward/Inverse Discrete Cosine Transform Engine (FIDCT) and Quantization /Inverse Quantization Engine, which are frequently used in video compression/decompression. For video encoding, DCT is used to reduce spatial redundancy of images. The quantization logic further filters most AC values and keeps the DC value. ...
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... DCT/IDCT Register RISC address/PCI Offset Address 0180H/0600H 0182H/0608H 0183H/060CH 0184H/0610H 0185H/0614H 0186H/0618H 0187H/061CH 0188H/0620H Winbond Confidential Name Read/Write Description Q_Control R/W Quantization value selection CBP threshold R/W CBP threshold value CheckSum R/W DCT result checksum EQuant value R/W Encoding loop Quant value ...
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... X_bus during bitstream receiving for decoding and bitstream transmission after encoding. Block Diagram X_BUS CPU BUS XDREQ_IPTF 1 CR1 INPUT DATA FIFO 1 CR2 P>S P<S 1 CT2 XDREQ_OPTF Winbond Confidential FM-R FM-T DREQ ENCF DREQ DECF VLD DECODER FIFO 1 CR3 1 CT1 BCH DECODE FIFO BCH S>P ...
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... RISC Address/PCI Offset Address 01A8H / 06A0H 01A9H / 06A4H 01AAH / 06A8H 01ABH / 06ACH 01ACH / 06B0H 01ADH / 06B4H 01AEH / 06B8H 01AFH / 06BCH Winbond Confidential Name Read/Write Description CDFIFO_H R/W Compressed Data FIFO High Word Register CDFIFO_L R/W Compressed Data FIFO Low Word Register ...
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... RISC Address / PCI Offset Address 01C0H / 0700H ................ 01FFH / 07FCH Winbond Confidential Name Read/Write Description MCR_L R/W Match Code Low Word Register MCR_H R/W Match Code High Word Register MSR ...
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... Audio Coprocessor Interface W9960CF provides an ADSP-21xx SPORT compatible serial port to interface to audio coprocessors. Multi-channel mode in AD SPORT0 is provided for interfacing with other chips time-division multiplexing (TDM) function. Transmitter FIFO and Receiver FIFO are used since serial one-bit bit stream is packed into 32-bit word, and no CPU instructions to access registers ...
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... INTRA/ INTER VLC Table VLE Result Register Tcoeff Result Register VLE Register RISC Address/PCI Offset Address 01B4H / 06D0H 01B5H / 06D4H 01B6H / 06D8H 01B7H / 06DCH Winbond Confidential DCT_Trig DCT/QUANT DCT_rdy RLC RLC_Trig Tcoeff-VLE ( Tcoeff FIFO overflow ) 16 x 32bit VLE_INT FIFO Bit Length Register ...
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... This ISA-like parallel I/O port provides an 8-bit data bus and 16-bit address bus to connect to co- processor easily. The host can access the connected co-processor through W9960CF PCI interface and this ISA-like interface. In this sense, W9960CF acts as a PCI to ISA bridge. It also provides two external interrupt requests of level or edge trigger. ...
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... ISA-Like Interface Resigisters RISC Address/PCI Offset Address 020H/080H 021H/084H 022H/088H 023H/08CH Programming Sequence W9960CF assert I/O read/write cycles on ISA-like interface accroding to the following programming sequence. IO Write Cycle Store ISACTL register (set WE bit enable) Store ISAADDR register (set effective address) Store ISADATA register ...
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... W9960CF REGISTERS 4.1 PCI Configuration Registers Address \ Bit 31 24 00H Device ID 04H Status 08H 0CH Reserved 10H 14H 18H - 38H 3CH Reserved Device/Vendor ID Register Read-only PCI Configuration Address: 00H Default: 9960 1050H Device Vendor ID Bits 31-16 Device ID Device ID allocated for the W9960 is 9960H. ...
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... RTA ( this bit will be clear the write data in the corresponding bit location Received Target Abort 1 = Target Abort Off Bit 27 STA ( this bit will be clear the write data in the corresponding bit location Signaled Target Abort 1 = Target Abort Off Bits 26-25 DEVSEL Timing ( Read only ) Winbond Confidential MDP FBC Reserved 10 9 ...
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... Bits 15-10 Reserved Bit 9 FBE Fast Back-to-Back Enable 1 = Enable 0 = Disable Bit 8 SERR# Enable 1 = Enable 0 = Disable Bit 7 Reserved Bit 6 PEE Parity Error Response Enable 1 = Enable 0 = Disable Bits 5-3 Reserved Bit 2 BME : Bus Master Enable 1 = Enable 0 = Disable Bit 1 MSE Winbond Confidential June 1997 ...
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... Bits 15-8 Programming Interface Bits 7-0 Revision ID Bits 31-8 are hardwired to 040000H to specify that the W9960 is a multimedia device. Header Type / Latency Timer Register Read-Write PCI Configuration Address: 0CH Default: 0000 FF00H Reserved Latency Timer Winbond Confidential Sub-Class Code Revision Header Type ...
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... This field can be used to relocate memory address space to any location that is aligned to 4 Kbytes for mapping W9960 Engine Registers and Data Memory. The low-order 12bits are read only and hardwired to 000H, the high-order 20bits are read- writable. Base Address 1 Register Read/Write PCI Configuration Address: 14H Default: 0000 0000H Base Address Winbond Confidential ...
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... Interrupt Pin Register Read-only PCI Configuration Address: 3DH Default: 01H Interrupt Pin Bits 7-0 Interrupt Line (hardwired to 01H) This register is hardwired specify that INTA# is the interrupt pin used. Winbond Confidential June 1997 ...
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... Output Low Voltage OL V Output High Voltage OH I Input Low Current IL I Input High Current IH I Output Tri-state Current OZ C Input Capacitance IN C Output Capacitance OUT I Power Supply Current CC 5.3 AC Specifications Winbond Confidential - 125 C -0. -0.5V to VDD+0. 5V, TA Min Typ Max Unit 0 ...
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... Parameter CLK Cycle Time t cyc CLK High Time t high t CLK Low Time low CLK Slew Rate 5.3 ESET IMING RST # Symbol Parameter t System reset active pulse width Low Winbond Confidential t cyc t high 0.6VDD t low 0.2VDD Min Max Min Max 10 t cyc ...
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... Note 1: bused signals : AD31-AD0, C/BE3-C/BE0, PAR, FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, PERR#, Note 2: point to point signals : REQ# is output signal, GNT# is input signal Note 3: Input Signal : IDSEL Note 4 : Output Signal : INTA#, SERR# Winbond Confidential 0.4VDD t val 0.285VDD (rising edge) 0.615VDD (falling edge) ...
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... DR/TFS/RFS Hold Time sch Ref. to SCLK falling TFS/RFS Valid Delay from SCLK rising t fsd t DT Valid Delay from SCLK rising scdv t DT Valid Delay from TFS tdv (Alternate Frame Mode) Winbond Confidential t sck 0.4VDD t t sch scs inputs 0.4VDD valid t fsd ...
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... CAS# valid delay ref. to CLK_MEM rising t cv2 t Memory address valid delay av Memory WE# valid delay Memory Data valid delay dv t Memory OE# valid delay ov Memory Data setup time t dsu t Memory Data hold time dh Winbond Confidential t cv1 t av Column Addr Column Addr Data Data dsu t dh Data Min 12 ...
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... GPIO AC T IMING CLK_MEM GPIO3-GPIO0 (Output) GPIO3-GPIO0 (Input) Symbol Parameter GPIO output access t AC time t GPIO input set up time SETUP GPIO input hold time t HOLD Winbond Confidential SETUP t HOLD Min Max Unit June 1997 ...
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... IDEO RE ROCESSOR CLK_Video t LLCH HREF, VS, HS, VD[15:0] Symbol Parameter t CLK_Video period LLC CLK_Video Low width t LLCL t CLK_Video High width LLCH Input Set Up time t SETUP t Input Hold Time HOLD Winbond Confidential IMING t LLC t LLCL t SETUP Min Typ HOLD Max Unit June 1997 ...
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... ISA IKE US IMING Waveform of IO Write Operation SAIOW# SAADDR15-0 SADATA7-0 Waveform of IO Read Operation SAIOR# SAADDR15-0 SADATA7-0 Winbond Confidential Address Data 50ns 150ns 80ns 150ns Address Data 50ns 20ns 0ns June 1997 ...
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... APPENDIXES 6.1 Porting Guide for W9960 Win95 Device Driver 6.2 Firmware Loading Precedure 6.3 Application/Firmware Command Block Winbond Confidential June 1997 ...