CXD3009Q Sony, CXD3009Q Datasheet
CXD3009Q
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CXD3009Q Summary of contents
Page 1
... CD Digital Signal Processor Description The CXD3009Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters, zero detection circuit, 1-bit DAC, and analog low-pass filter on a single chip. Features Digital Signal Processor (DSP) Block • Playback mode supporting CAV (Constant Angular Velocity) – ...
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... Interface Sequencer CNIN Error Corrector EFM Interface demodurator 16K RAM Digital CLV – 2 – D/A Serial-In Interface Timing Logic Over Sampling Digital Filter 3rd-Order Digital Noise Shaper OUT PWM PWM CXD3009Q 24 TES1 TEST 23 79 XRST RMUT 3 2 LMUT 70 XTAI XTAO 71 65 ...
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... Pin Configuration SYSM 62 AVss AOUT1 65 66 AIN1 LOUT1 67 AVss XTAI 70 XTAO 71 XVss 72 AVss 73 LOUT2 74 AIN2 75 AOUT2 AVss 78 XRST – 3 – LRCKI 39 LRCK 38 ASYO 37 ASYI 36 BIAS CLTV 32 AVss 31 FILI 30 FILO PCO 29 28 VCTL 27 V16M 26 VCKI 25 VPCO 24 TES1 23 TEST PWMI 22 21 MDP CXD3009Q ...
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... VCO2 control voltage input for the wide-band EFM PLL. Master PLL charge pump output. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Analog GND. Master VCO control voltage input. Analog power supply (+3V). EFM signal input. – 4 – Description CXD3009Q ...
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... Analog power supply (+3V). Left-channel analog output. Left-channel operational amplifier input. Left-channel LINE output. Analog GND. Power supply for master clock. Crystal oscillation circuit input. Input the external master clock via this pin. Crystal oscillation circuit output. – 5 – Description , high = CXD3009Q ...
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... XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin. GND for master clock. Analog GND. Right-channel LINE output. Right-channel operational amplifier input. Right-channel analog output. Analog power supply (+3V). Analog GND. System reset. Reset when low. Power supply (+3V). – 6 – Description CXD3009Q ...
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... Analog input Vss IN V (1) V – 0 –4mA ( 4mA (2) V – 0 –2mA ( 4mA (4) V – 0 –0.28mA ( 0.36mA – 3.60V – 3.60V LO O and AV , respectively – 7 – CXD3009Q = AV = 0V, Topr = –20 to +75°C) SS Applicable Typ. Max. Unit pins µ µA ...
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... Input amplitude 3.3V ± 5 Min. Typ. Max. Unit 7 34 MHz = AV = 3.3V ± 5 Min. Typ. Max. Unit ns 13 500 13 500 ns ns 1,000 26 0. WLX WHX 3.3V ± 5 Min. Typ. Max. Unit 0. 0.3 Vp – 8 – IHX V 0.9 IHX 0.1 IHX V ILX CXD3009Q ...
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... Topr = –20 to +75° Min. Typ. Max. 0.65 750 300 300 300 750 0.65 750 1 WCK WCK 1 3.3V ± 5 Symbol Conditions Min (BCKI) t (BCKI (PCMDI) (PCMDI) t (LRCKI) – 9 – Unit MHz MHz 0V, Topr = –20 to +75° Typ. Max. Unit CXD3009Q ...
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... Analog Characteristics (V DD Conditions Crystal 384Fs 768Fs 384Fs 768Fs 12k 680p 12k 12k 22µ LPF External Circuit Diagram 768Fs/384Fs Rch RF CXD3009Q Lch – 10 – 3.3V 0V 25° Typ. Max. Min. 0.015 0.025 0.015 0.025 SHIBASOKU (AM51A) Audio Analyzer 100k A Audio Analyzer B CXD3009Q Unit % dB ...
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... Item Symbol Output voltage V OUT Load resistance R Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is output. Applicable pins 1 LOUT1, LOUT2 ( 3.3V Min. Typ. 0. – 11 – = 0V, Topr = – +75°C) SS Max. Unit Applicable pins Vrms CXD3009Q ...
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... Information on each address and the data is provided in Table 1-1. • The internal registers are initialized by a reset when XRST is low; the initialization data is shown in Table 1-2. Note) When XLAT is low, SQCK must be set high Data Address – 12 – CXD3009Q D3 750ns or more Valid 300ns max ...
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... Register – 13 – CXD3009Q ...
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... Register – 14 – CXD3009Q ...
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... The number of tracks jumped is counted according to the signals input from the CNIN pin. AS2 AS1 AS0 RXF RXF RXF RXF RXF = 0 FORWARD RXF = 1 REVERSE 0.09ms 0.02ms 0.05ms 0.18ms 0.09ms 0.05ms 5.8ms 2.9ms 1.45ms Data 1 Data – 15 – Data 3 Data CXD3009Q ...
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... Audio mode; average value interpolation and pre-value hold are performed. Processing Processing 1 Anti-rolling is enhanced. Sync window protection is enhanced. – 16 – Data VCO KSL3 KSL2 KSL1 SEL2 See the $BX commands. Data TXON TXOUT OUTL1 OUTL0 Processing Application CXD3009Q D1 D0 KSL0 D1 D0 ...
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... Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. Wide-band PLL VCO2 is set to high speed frequency-divided. – 17 – CXD3009Q 1 , and the output is 1 and the output is 1 and the output is 1 and the output is 1/8 ...
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... PCMD, BCK, LRCK and EMPH outputs are set to low. OUTL0 = 1 PCMD and PCMDI, BCK and BCKI, LRCK and LRCKI, EMPH and EMPHI are connected inside the IC, respectively. At this time, set PCMDI = BCKI = LRCKI = EMPHI = low. Processing Processing Processing Processing Processing – 18 – CXD3009Q ...
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... CXD3009Q ...
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... Data 2 D0 and subsequent data are DF/DAC function settings. Data 2 Data 000 SYCOF 0 MCSL OPSL1 Data 2 D0 and subsequent data are DF/DAC function settings. Data 3 Data 000 SYCOF 1 MCSL OPSL1 Processing Processing Processing Processing – 20 – CXD3009Q Data ZDPL ZMUT — Data — — — Data ZDPL ZMUT 0 Data 5 ...
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... Data 2 and subsequent data are DF/DAC function settings. Data ATT EMPH OPSL2 Data 4 Data AD6 AD5 AD4 AD3 AD2 – 21 – Data SMUT AD10 Data — — — AD1 AD0 Data SMUT AD10 Data AD1 AD0 FMUT LRWO BSBST BBSL CXD3009Q D0 — D0 ...
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... Meaning Audio output The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways. 0dB The audio output from 001h to 400h is obtained using the –0.0085dB following equation. –0.017dB Audio output = 20log –60.206dB – – 22 – CXD3009Q Attenuation data [dB] 1024 ...
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... However, synchronization can be forcibly performed by setting LRWO = 1. Command bit BSBST = 1 Bass boost is on. BSBST = 0 Bass boost is off. BSBST can be set when OPSL2 = 1. Command bit BBSL = 1 Bass boost is Max. BBSL = 0 Bass boost is Mid. BBSL can be set when OPSL2 = 1. Meaning Meaning Note) Processing Processing – 23 – CXD3009Q ...
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... CXD3009Q ...
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... L0 and R0 are LSB. C1F1 C1F2 C1 correction status Error 1 0 Single Error Correction 1 1 Irretrievable Error Command bit CPUSR = 1 XLON pin is high. CPUSR = 0 XLON pin is low. Description C2F1 C2F2 Error 1 0 Single Error Correction 1 1 Irretrievable Error Processing – 25 – CXD3009Q C2 correction status ...
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... Monitor output switching The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B. Pin No. Command bit MTSL1 MTSL0 Mode description 47 48 XUGF XPCK MNT1 MNT0 RFCK XPCK – 26 – GFS C2PO MNT3 C2PO XROF GTOP CXD3009Q ...
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... CLVP mode gain setting: GMDP: GMDS Gain Gain GMDP MDP1 MDP0 0 0 –6dB 0 1 0dB 1 0 +6dB Gain Gain Gain MDS1 MDS0 MDP0 Gain CLVS GCLVS –12dB –6dB –6dB 0dB 0dB +6dB Gain MDS1 – 27 – Gain GMDS MDS0 0 –6dB 1 0dB 0 +6dB CXD3009Q ...
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... The rotational velocity R of the spindle can be expressed with the following equation. Description to R: Relative velocity at normal speed = 1 n: VP0 to 7 setting value F0 VP0 to 7 setting value [HEX] Fig. 1-1 – 28 – Data VP4 VP3 VP2 VP1 256 – CXD3009Q D1 D0 VP0 ...
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... VC2C HIFC LPWR VPON – 29 – Data SFSL VC2C HIFC LPWR VPON Description Mode Description CLV-N Crystal reference CLV servo. Used for normal-speed CLV-W playback in CLV-W mode. CAV-W Spindle control with VP0 to 7. Spindle control with the external CAV-W PWM. CXD3009Q ...
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... KICK 1-3 (a) BRAKE 1-3 (b) STOP 1-3 (c) KICK 1-4 (a) BRAKE 1-4 (b) STOP 1-4 (c) KICK 1-5 (a) BRAKE 1-5 (b) STOP 1-5 (c) KICK 1-6 (a) BRAKE 1-6 (b) STOP 1-6 (c) Timing chart 1-7 1-8 1-9 1-10 (EPWM = 0) 1-11 (EPWM = 0) 1-12 (EPWM = 1) 1-13 (EPWM = 1) – 30 – CXD3009Q ...
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... CAV-W mode LPWR = 1 KICK H MDP (a) KICK BRAKE Z MDP L (b) BRAKE BRAKE Z MDP L (b) BRAKE BRAKE Z MDP (b) BRAKE BRAKE MDP L (b) BRAKE BRAKE Z MDP (b) BRAKE – 31 – CXD3009Q STOP Z MDP (c) STOP STOP Z MDP (c) STOP STOP Z MDP (c) STOP STOP Z MDP (c) STOP STOP Z MDP (c) STOP ...
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... CAV-W mode EPWM = LPWR = 0 Acceleration MDP 264kHz 3.8µs Timing Chart 1-11 CAV-W mode EPWM = LPWR = 1 Acceleration MDP 264kHz 3.8µs n · 236 (ns The BRAKE pulse is masked when LPWR = 1. The BRAKE pulse is masked when LPWR = 1. – 32 – CXD3009Q Z Deceleration Z Deceleration Z Z Deceleration Z ...
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... Timing Chart 1-12 CAV-W mode EPWM = 1, LPWR = 0 H PWMI L H MDP L Timing Chart 1-13 CAV-W mode EPWM = LPWR = 1 H PWMI MDP Acceleration Acceleration The BRAKE pulse is masked when LPWR = 1. – 33 – CXD3009Q Deceleration ...
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... This section explains the subcode interface. There are two methods for reading out a subcode externally. The 8-bit subcodes can be read from SBSO by inputting EXCK to the CXD3009Q. Sub Q can be read out after checking the CRC of the 80bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high ...
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... Timing Chart 2-1 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO S0· Same 400ns max S0 · S0· Same Sub Code P.Q.R.S.T.U.V.W Read Timing – 35 – CXD3009Q ...
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... CXD3009Q ...
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... Relative velocity, m: Measurement results) 32 VF0 the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). Load m – 38 – CXD3009Q ...
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... Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc (excluding DATO, CLKO and XLTO). Note) The capture range for this mode is theoretically up to the signal processing limit. – 39 – CXD3009Q ...
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... Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode CLV-W Mode CLV-W CLVP CLV-W MODE START KICK $E8000 Mute OFF $A0XXXXX CAV-W $E6650 (CLVA) NO ALOCK = H ? YES CLV-W $E60C0 (CLVA) (WFCK PLL) YES ALOCK = Fig. 3-2. CLV-W Mode Flow Chart – 40 – CXD3009Q Operation mode Spindle mode Time ...
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... EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3009Q has a built-in three-stage PLL. • The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. ...
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... Spindle rotation information 1/2 1/32 1/2 1/n Microcomputer 256 control (VP7 to 0) 1/K (KSL1, 0) VPON 1/M 1/N 1/K (KSL3, 2) RFPLL CXD3009Q – 42 – CXD3009Q CLV-W CAV-W VPCO CLV-N CLV-W CAV-W /CLV-N LPF VCOSEL2 VCTL VCO2 V16M VCKI PCO FILI FILO CLTV VCO1 VCOSEL1 ...
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... For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD3009Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to achieve high playability. • The correction status can be monitored externally. ...
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... MNT3 C1 correction MNT1 MNT0 4-4. DA Interface • The CXD3009Q DA interface is as described below. This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. C2 correction Strobe – 44 – ...
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... CXD3009Q ...
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... There are three Digital Out formats: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3009Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits the channel status ...
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... XLTO Fig. 4-2. Auto focus Focus search up FOK = H NO YES FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 4-3-(a). Auto Focus Flow Chart – 47 – CXD3009Q Microcomputer (Checks whether FZC is continuously high for the period of time E set with register 5) ...
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... Fig. 4-7. N can be set to 216 tracks. CNIN is used for counting the number of jumps. This N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. Blind E Fig. 4-3-(b). Auto Focus Timing Chart – 48 – CXD3009Q $08 16 tracks, ...
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... REV jump) sled servo OFF WAIT (Blind A) CNIN = NO YES Track REV (FWD kick for REV jump) kick WAIT (Brake B) Track, sled servo ON END Fig. 4-4-(a). 1-Track Jump Flow Chart $2C ($28) Fig. 4-4-(b). 1-Track Jump Timing Chart – 49 – CXD3009Q Brake B $25 ...
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... CNIN (Blind A) CNIN = YES Track, REV kick C = Overflow ? NO YES Track, sled servo ON END Fig. 4-5-(a). 10-Track Jump Flow Chart CNIN 5 count Fig. 4-5-(b). 10-Track Jump Timing Chart – 50 – 5) (Checks whether the CNIN cycle is longer than overflow C) Overflow C $2E ($2B) CXD3009Q $25 ...
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... Track, sled FWD kick WAIT (Blind A) CNIN = N NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 4-6-(a). 2N-Track Jump Flow Chart CNIN N count $2E ($2B) Fig. 4-6-(b). 2N-Track Jump Timing Chart – 51 – CXD3009Q Kick D Overflow $26 ($27) $25 ...
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... Blind A Command for SSP $22 ($23) N Track move Track servo OFF Sled FWD kick WAIT (Blind A) CNIN = N NO YES Track, sled servo OFF END END Fig. 4-7-(a). N-Track Move Flow Chart CNIN N count Fig. 4-7-(b). N-Track Move Timing Chart – 52 – CXD3009Q $20 ...
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... Gain MDS Over Sampling Filter-2 Noise Shape Modulation PWMI Mode Select LPWR MDP Spindle drive signal from the microcomputer for CAV servo Fig. 4-8. Block Diagram – 53 – MDP Error Measure Over Sampling Filter-1 Gain MDP 1/2 MUX CLV P/S CXD3009Q ...
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... LSB first. • The data which can be stored in the IC is for 1 packet (4 packs). Subcode Decoder Fig. 4-10. CD-TEXT Demodulation Circuit Block Diagram CXD3009Q R2 CD-TEXT Decoder TXON TXOUT – 54 – ASYO 47 R1 ASYI EXCK SBSO SQCK SQSO CXD3009Q ...
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... Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First sent, followed by X2 sent before X1 reaches the figure), X1 continues approaching Y2. Next sent before X1 reaches the figure), X1 then approaches Y3 from the value ( the figure) at that point. 0dB 7F ( – 00 (H) 23.2 [ms] – 56 – CXD3009Q ...
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... When setting FMUT, set OPSL2 to 1. (See the $AX commands.) Zero detection mute Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) Soft mute on 23.2 [ms] – 57 – CXD3009Q Soft mute off 23.2 [ms] ...
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... See Graph 5-2 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 –14. 100 300 1k Digital Bass Boost Frequency Response [Hz] Graph 5-2. – 59 – CXD3009Q Normal DBB MID DBB MAX 3k 10k 30k ...
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... LPF Block The CXD3009Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency determined flexibly. The reference voltage ( (AV C The LPF block application circuit is shown below. ...
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... Setting Method of the CXD3009Q Playback Speed (in CLV-N mode) (A) CD-DSP block The playback modes shown below can be selected by the combination of the crystal, XTSL pin and DSPB command of $9X. CD-DSP block playback speed X'tal XTSL 768Fs 1 768Fs 1 384Fs 0 384Fs 0 384Fs 44.1kHz 1 Low power consumption mode. The CD-DSP processing speed is halved, allowing the power consumption to be decreased ...
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... EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 0.6g + 0.35 1.5 – 0.15 0 0.15 0.1 – 0.1 0˚ to 10˚ EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.6g CXD3009Q ...
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... DETAIL A DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SONY CODE QFP-80P-L052 P-QFP80-14X14-0.65 LEAD MATERIAL EIAJ CODE JEDEC CODE PACKAGE MASS – 64 – 1.6MAX 1 0 EPOXY RESIN SOLDER PLATING 42 ALLOY 1.6 g CXD3009Q Sony Corporation ...