MC14522BCP Freescale Semiconductor, Inc, MC14522BCP Datasheet

MC14522BCP

Manufacturer Part Number

MC14522BCP

Description

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MC14522BCP.pdf (10 pages)

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Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Presettable 4-Bit Down Counters

constructed with MOS P–channel and N–channel enhancement mode

devices in a monolithic structure.

with a decoded “0” state output for divide–by–N applications. In single stage

applications the “0” output is applied to the Preset Enable input. The

Cascade Feedback input allows cascade divide–by–N operation with no

additional gates required. The Inhibit input allows disabling of the pulse

counting function. Inhibit may also be used as a negative edge clock.

ers, phase–locked loops, and other frequency division applications requiring

low power dissipation and/or high noise immunity.

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

X = Don’t Care

NOTES:

REV 3

1/94

MAXIMUM RATINGS*

V in , V out

Clock Reset

** Output “0” is high when reset is low, only if CF is high and count is 0000.

Symbol

MOTOROLA CMOS LOGIC DATA

I in , I out

* Output “0” is low when reset goes high only it PE and CF are low.

The MC14522B BCD counter and the MC14526B binary counter are

These devices are presettable, cascadable, synchronous down counters

These complementary MOS counters can be used in frequency synthesiz-

Motorola, Inc. 1995

V DD

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Logic Edge–Clocked Design — Incremented on Positive Transition of

Clock or Negative Transition of Inhibit

Asynchronous Preset Enable

Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

T stg

P D

T L

Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C

Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C

DC Supply Voltage

Input or Output Voltage (DC or Transient)

Input or Output Current (DC or Transient),

per Pin

Power Dissipation, per Package†

Storage Temperature

Lead Temperature (8–Second Soldering)

Inhibit

Inputs

(Voltages Referenced to V SS )

Enable

Preset

Parameter

FUNCTION TABLE

Feedback

Cascade

Output

“0”

– 0.5 to V DD + 0.5

– 0.5 to + 18.0

Asynchronous reset*

Asynchronous reset

Asynchronous preset

Decrement inhibited

No change** (inactive edge)

Decrement**

– 65 to + 150

Value

500

260

Resulting

Function

Unit

_ C

guard against damage due to high static

voltages or electric fields. However, pre-

cautions must be taken to avoid applications of

any voltage higher than maximum rated volt-

ages to this high–impedance circuit. For proper

operation, V in and V out should be constrained

to the range V SS

appropriate logic voltage level (e.g., either V SS

or V DD ). Unused outputs must be left open.

This device contains protection circuitry to

Unused inputs must always be tied to an

T A = – 55 to 125 C for all packages.

INHIBIT

CLOCK

ORDERING INFORMATION

MC14XXXBCP

MC14XXXBCL

MC14XXXBDW

MC14522B

MC14526B

V SS

PIN ASSIGNMENT

MC14522B MC14526B

(V in or V out )

DW SUFFIX

CASE 751G

CERAMIC

CASE 620

CASE 648

L SUFFIX

P SUFFIX

V DD

“0”

RESET

PLASTIC

Plastic

Ceramic

SOIC

V DD .

Related parts for MC14522BCP

MC14522BCP Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Presettable 4-Bit Down Counters The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. These devices are presettable, cascadable, synchronous down counters with ...

Page 2

Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 3

Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...

Page 4

– RESET Q3 INHIBIT CLOCK “0” EXTERNAL V SS POWER SUPPLY Figure 1. Typical Output Source Characteristics Test Circuit ...

Page 5

CLOCK 50% 10 1/f max t PLH t PHL 90% ANY Q 50% OR “0” 10% t TLH t THL Figure 90% ANY P 50% 10% t PLH ...

Page 6

Preset Enable (Pin 3) — If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3. Inhibit (Pin 4) — A high level on the ...

Page 7

MC14522B LOGIC DIAGRAM (BCD Down Counter INHIBIT CLOCK 6 10 RESET MC14526B LOGIC DIAGRAM (Binary Down Counter ...

Page 8

Divide–By–N, Single Stage Figure 11 shows a single stage divide–by–N application. The MC14522B (BCD version) can accept a number greater than 9 and count down in binary fashion. Hence, the BCD and binary single stage divide–by–N counters (as shown in ...

Page 9

N SEATING PLANE 0.25 (0.010 –A– 0.25 (0.010) M MOTOROLA CMOS LOGIC ...

Page 10

D 16X 0.010 (0.25 –T– SEATING G 14X K PLANE Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no ...

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