AD9244 Analog Devices, AD9244 Datasheet
AD9244
Specifications of AD9244
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AD9244 Summary of contents
Page 1
... Out of Range (OTR)—The OTR output bit indicates when the input signal is beyond the AD9244’s input range. Single Supply—The AD9244 uses a single +5V power sup- ply simplifying system power supply design. It also features a separate digital output driver supply line to accommodate 3V and 5V logic families ...
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... Full IV 2.7 3.0 3.6 Full IV 104 +25°C I Full IV 12 +25°C I Full V Full VI 590 – 2 – AD9244BST-40 Min Typ Max Units 14 bits 14 bits %FSR %FSR LSB ±0.6 LSB LSB ±1.3 LSB ppm/°C ppm/°C ±3.9 mV ±2.79 mV 0.79 LSB rms ...
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... V -80 Full V -90 Full V -83 Full V -83 Full V -82 Full VI +25° +25° +25° +25° – 3 – AD9244BST-40 Min Typ Max Units 75 dBc 75 dBc dBc 71 dBc 75 dBc 74 dBc dBc 70 dBc -92 dBc -82 dBc dBc -74 dBc -97 -79 -77 95 dBc 82 dBc dBc ...
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... The clock period may be extended with no degradation in specified performance at +25°C. 2 For the AD9244-65 only, with duty cycle stabilizer enabled. DCS function not applicable for -40 model. 3 Output delay is measured from clock 50% transition to data 50% transition, with 5pF load on each output. 4 Wake-up time is dependent on value of decoupling capacitors, typical values shown with 0.1 F and 10 F capacitors on REFT and REFB. ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9244 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recom- mended to avoid performance degradation or loss of functionality ...
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... AGND CLK- CLK+ NC OEB DB0 (LSB) DB1 DB2 REV. PrD 01/22/02 DRGND for straight binary DRVDD for 2’s complement (0.5*AVDD AD9244 6 48 LQFP 7 (Pr elim inar y and not to scale – 6 – REF SENSE 36 DFS 35 AVDD 34 33 AGND AGND 32 31 AVDD 30 DRGND ...
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... PRELIMINARY TECHNICAL DATA AD9244–SPECIFICATIONS DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” ...
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... TYPICAL PERFORMANCE CHARACTERISTICS - AD9244 (AVDD = 5.0V, DRVDD = 3.0V 65MSPS with CLK Duty Cycle Stabilizer Enabled, T SAMPL E length = 8K, unless otherwise noted) TPC1. Single Tone 8K FFT 5MHz IN TPC3. Single Tone 8K FFT 31MHz IN TPC5. 3rd Order Intermodulation Distortion vs. Fin1,Fin2 at Ain1,Ain2=-6.5dBFS. Spacing be- tween Fin1 and Fin2 = 1MHz. ...
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... TPC7. SINAD/ENOB vs. Frequency TPC8. THD vs. Frequency TPC9. SNR vs. Temperature and Frequency REV. PrD 01/22/02 TYPICAL PERFORMANCE CHARACTERISTICS - AD9244 =25°C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT A TPC10. SNR vs. Frequency TPC11. SFDR vs. Frequency TPC12. THD vs. Temperature and Frequency ...
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... TYPICAL PERFORMANCE CHARACTERISTICS - AD9244 (AVDD = 5.0V, DRVDD = 3.0V 65MSPS with CLK Duty Cycle Stabilizer Enabled, T SAMPL E length = 8K, unless otherwise noted) TPC13. Harmonics vs. Frequency TPC14. SFDR vs. Sample Rate TPC15. Typical INL REV. PrD 01/22/02 =25°C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT A TPC16 ...
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... IN1 70.6MHz TPC21. Dual-Tone 8K FFT, f IN1 and f = 140.7MHz IN2 REV. PrD 01/22/02 TYPICAL PERFORMANCE CHARACTERISTICS - AD9244 =25°C, Differential Input Span, , VCM = 2.5V, AIN = -0.5dBFS, VREF = 2.0V, FFT A TPC22. Dual Tone SNR and SFDR, f IN2 and f IN2 TPC23. Dual-Tone SNR and SFDR, f ...
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... TYPICAL PERFORMANCE CHARACTERISTICS - AD9244 (AVDD = 5.0V, DRVDD = 3.0V 65MSPS with CLK Duty Cycle Stabilizer Enabled, T SAMPL E length = 8K, unless otherwise noted) TPC25. Single Tone 8K FFT 190.82MHz (typical WCDMA carrier), f SAMPLE TPC26. Dual-Tone 8K FFT, f IN1 240.7MHz TPC27. CMRR vs. Frequency ( 2.5V REV. PrD 01/22/02 =25° ...
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... TPC32. Undersampling Performance of AD9244, Driving ADC Inputs with Transformer and Balun REV. PrD 01/22/02 TYPICAL PERFORMANCE CHARACTERISTICS - AD9244 AD9244 - SINAD/SFDR vs =190 MHz IN IN -19 - -dBFS IN =65MSPS, Driving ADC Inputs with Transformer and Balun CLK AD9244 - SNR/SFDR vs ...
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... This latency is not a concern in many applications. The digital output, together with the out-of- range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9244 can be configured to interface with +5V or +3V logic families. Connecting the DUTY pin to AVDD implements the internal clock stabilization function in the AD9244 ...
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... PRELIMINARY TECHNICAL DATA For noise sensitive applications, the very high bandwidth of the AD9244 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the ADC’s input by forming a low pass filter. The source impedance driving VIN+ and VIN- should be matched ...
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... USING THE INTERNAL REFERENCE The AD9244 can be easily configured for either a 1V p-p differential input span or 2V p-p input span by setting the internal reference. Other input spans can be realized with two external gain-setting resistors as shown in Figure 6 of this data sheet, or using an external reference ...
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... BSC 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.053 (1.35) 0.018 (0.45) 48 0.006 (0.15) 1 0.002 (0.05) TOP VIEW (PINS DOWN MIN 0.007 (0.2) 0.011 (0.27) 0.019 (0.5) 0.004 (0.09) BSC 0.006 (0.17) 17 AD9244 37 36 0.276 0.354 (7.0) (9.00) BSC BSC 25 24 ...