XPC860TZP50D3 Motorola, XPC860TZP50D3 Datasheet
XPC860TZP50D3
Related parts for XPC860TZP50D3
XPC860TZP50D3 Summary of contents
Page 1
... It particularly excels in both communications and networking systems. The PowerQUICC unit is referred to as the MPC860 in this manual. The MPC860 is a derivative of Motorola’s MC68360 Quad Integrated Communications Controller (QUICC implements the PowerPC architecture. The CPU on the MPC860 is a 32-bit ™ ...
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... MPC860 Family Hardware Specifications 2 C) channel. The memory controller has been enhanced, Table 1. MPC860 Family Functionality Ethernet Data Cache 10T 10/100 — — — ATM SCC Ref. — yes 2 1,2,3 yes 2 1,2,3 — yes 4 1,2 yes 4 1,2,3 yes 4 1,2,3 yes 1 4 MOTOROLA ...
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... Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture • System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer MOTOROLA MPC860 Family Hardware Specifications Features 3 ...
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... RISC communications processor (CP) — Communication-specific commands (for example, ENTER HUNT MODE — Supports continuous mode transmission and reception on all serial channels — 8Kbytes of dual-port RAM — 16 serial DMA (SDMA) channels 4 MPC860 Family Hardware Specifications , and ) RESTART TRANSMIT , GRACEFUL STOP TRANSMIT MOTOROLA ...
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... Multiple-master environment support • Time-slot assigner (TSA) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 8-bit resolution MOTOROLA MPC860 Family Hardware Specifications Features 5 ...
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... Reliability of operation is enhanced, if unused inputs are tied to an appropriate logic voltage level (for example, either GND MPC860 Family Hardware Specifications ). dd MOTOROLA ...
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... Air Flow (200 ft/min) 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. MOTOROLA MPC860 Family Hardware Specifications Symbol V DDH V DDL ...
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... MPC860 Family Hardware Specifications 1 Frequency (MHz) Typical 25 450 40 700 50 870 33 375 50 575 66 750 50 656 66 TBD 66 722 80 851 NOTE -based power dissipation DDL ) D 2 Maximum Unit 550 mW 850 mW 1050 mW TBD mW TBD mW TBD mW 735 mW TBD mW 762 mW 909 mW . I/O power DDH MOTOROLA ...
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... Drain Pins) Output Low Voltage IOL = 2.0 mA, CLKOUT 2 IOL = 3 IOL = 5.3 mA IOL = 7.0 mA, TXD1/PA14, TXD2/PA12 IOL = 8.9 mA, TS, TA, TEA, BI, BB, HRESET, SRESET 1 Input capacitance is periodically sampled. MOTOROLA MPC860 Family Hardware Specifications Symbol Min VDDSYN 3.0 DDH DDL KAPWR 2.0 (power-down mode) ...
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... Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θJA θJC 10 MPC860 Family Hardware Specifications × PI/O, where PI/O is the power °C can be obtained from the equation: J × θCA – MOTOROLA ...
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... Figure 7- Board Temperature Rise Above Ambient Divided by Package Power Board Temperture Rise Above Ambient Divided by Package Figure 7-1. Effect of Board Temperature Rise on Thermal Behavior MOTOROLA MPC860 Family Hardware Specifications Estimation with Junction-to-Board Thermal Resistance For instance, the user θ ...
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... A small amount of epoxy is placed over the thermocouple junction and over about wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 12 MPC860 Family Hardware Specifications × × can be used to determine the MOTOROLA ...
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... The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus). MOTOROLA MPC860 Family Hardware Specifications and GND should be kept to less than half an inch per DD and GND circuits ...
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... DP(0:3) valid (hold time) B22 CLKOUT rising edge to CS asserted GPCM ACS = 00 B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 B22b CLKOUT falling edge to CS asserted GPCM ACS = 11, TRLX = 0, EBDF = 0 MOTOROLA MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max Min Max Min 7 ...
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... ACS = 10, or ACS = 11, EBDF = 0 B30b WE(0:3) negated to A(0:31), invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31), Invalid GPCM, write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 MOTOROLA MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max Min ...
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... Unit Max Min Max — 2.68 — ns — 17.83 — ns 6.00 1.50 6.00 ns 11.75 3.80 10.54 ns 8.00 1.50 8.00 ns 11.75 3.80 10.04 ns 14.13 7.58 12.31 ns 6.00 1.50 6.00 ns 11.75 3.80 10.54 ns 8.00 1.50 8.00 ns 11.75 3.80 10.54 ns 14.13 7.58 12.31 ns MOTOROLA ...
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... UPWAIT valid to CLKOUT falling 9 edge B38 CLKOUT falling edge to UPWAIT 9 valid B39 AS valid to CLKOUT rising edge B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT rising edge MOTOROLA MPC860 Family Hardware Specifications 33 MHz 40 MHz Min Max Min Max 1.50 6.00 1.50 6.00 7 ...
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... MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max Min Max Min 7.00 — 7.00 — 7.00 2.00 — 2.00 — 2.00 — TBD — TBD — 66 MHz Unit Max Min Max — 7.00 — ns — 2.00 — ns TBD — TBD ns MOTOROLA ...
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... Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 9-3 provides the timing for the external clock. CLKOUT Figure 9-3. External Clock Timing MOTOROLA MPC860 Family Hardware Specifications 0 2 ...
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... Figure 9-5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT TS, BB TA, BI TEA Figure 9-5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals 22 MPC860 Family Hardware Specifications B8 B9 B8a B9 B8b B11 B12 B11a B12a B14 B15 Timing B13 B13a MOTOROLA ...
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... Figure 9-8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) MOTOROLA MPC860 Family Hardware Specifications B16 B17 ...
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... Figure 9-9 through Figure 9-12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx OE WE[0:3] D[0:31], DP[0:3] Figure 9-9. External Bus Read Timing (GPCM Controlled—ACS = 00) 24 MPC860 Family Hardware Specifications B20 B21 and DLT3 = 1 B12 B25 B28 B18 B23 B26 B19 MOTOROLA ...
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... Figure 9-10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] CSx OE D[0:31], DP[0:3] Figure 9-11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MOTOROLA MPC860 Family Hardware Specifications B12 B23 B22a B24 B25 B18 B12 B22b B22c ...
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... Figure 9-12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, Figure 9-13 through Figure 9-15 provide the timing for the external bus write controlled by various GPCM factors. 26 MPC860 Family Hardware Specifications B12 B8 B22a B27 B27a B22b B22c B18 ACS = 11) B23 B26 B19 MOTOROLA ...
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... CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] OE D[0:31], DP[0:3] Figure 9-13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MOTOROLA MPC860 Family Hardware Specifications B12 B25 B26 B8 Bus Signal Timing B30 B23 B28 B29b B29 B9 27 ...
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... Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] OE D[0:31], DP[0:3] Figure 9-14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) 28 MPC860 Family Hardware Specifications B12 B28b B28d B25 B26 B28a B28c B8 B30a B30c B23 B29c B29g B29a B29f B9 MOTOROLA ...
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... A[0:31] CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 9-15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) Figure 9-16 provides the timing for the external bus controlled by the UPM. MOTOROLA MPC860 Family Hardware Specifications B12 B8 B22 B28b B28d B25 B8 B28a B28c ...
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... Figure 9-16. External Bus Timing (UPM Controlled Signals) Figure 9-17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. 30 MPC860 Family Hardware Specifications B31a B31d B31 B31b B34 B34a B34b B32a B32d B32 B32b B36 B35a B35b B33 B31c B32c B33a MOTOROLA ...
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... CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 9-18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Figure 9-19 provides the timing for the synchronous external master access controlled by the GPCM. MOTOROLA MPC860 Family Hardware Specifications B38 Timing B38 Timing Bus Signal Timing 31 ...
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... A[0:31], TSIZ[0:1], R/W CSx Figure 9-20. Asynchronous External Master Memory Access Timing Figure 9-21 provides the timing for the asynchronous external master control signals negation. 32 MPC860 Family Hardware Specifications B41 B42 B40 00) B39 B40 (GPCM Controlled—ACS = 00) B22 B22 MOTOROLA ...
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... Figure 9-22 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT IRQx Figure 9-22. Interrupt Detection Timing for External Level Sensitive Lines Figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines. MOTOROLA MPC860 Family Hardware Specifications B43 Table 9-7. Interrupt Timing 1 4 × ...
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... A[0:31] REG CE1/CE2 PCOE, IORD ALE D[0:31] Figure 9-24. PCMCIA Access Cycles Timing External Bus Read Figure 9-25 provides the PCMCIA access cycle timing for the external bus write. MOTOROLA MPC860 Family Hardware Specifications P44 P46 P45 P48 P50 P52 ...
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... Figure 9-26 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 9-26. PCMCIA WAIT Signals Detection Timing Table 9-9 shows the PCMCIA port timing for the MPC860. 36 MPC860 Family Hardware Specifications P44 P46 P45 P48 P50 P52 P53 B8 P55 P56 P47 P49 P51 P54 P52 B9 MOTOROLA ...
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... Figure 9-28 provides the PCMCIA output port timing for the MPC860. CLKOUT Input Signals Figure 9-28. PCMCIA Input Port Timing Table 9-10 shows the debug port timing for the MPC860. MOTOROLA MPC860 Family Hardware Specifications Table 9-9. PCMCIA Port Timing 33 MHz 40 MHz Min ...
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... MPC860 Family Hardware Specifications Table 9-10. Debug Port Timing 3 × T 1.25 × T D61 D62 D61 D64 D65 D66 D67 All Frequencies Min Max — CLOCKOUT — CLOCKOUT 0.00 3.00 8.00 — 5.00 — 0.00 15.00 0.00 2.00 D62 D63 MOTOROLA Unit — — ...
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... R80 DSDI, DSCK setup R81 DSDI, DSCK hold time R82 SRESET negated to CLKOUT rising edge for DSDI and DSCK sample Figure 9-31 shows the reset timing for the data bus configuration. MOTOROLA MPC860 Family Hardware Specifications Table 9-11. Reset Timing 33 MHz 40 MHz ...
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... D[0:31] (OUT) (Weak) Figure 9-32. Reset Timing—Data Bus Weak Drive During Configuration Figure 9-33 provides the reset timing for the debug port configuration. 40 MPC860 Family Hardware Specifications R71 R76 R73 R74 R75 R69 R79 R77 R78 MOTOROLA ...
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... TCK falling edge to output valid out of high impedance J94 TCK falling edge to output high impedance J95 Boundary scan input valid to TCK rising edge J96 TCK rising edge to boundary scan input invalid MOTOROLA MPC860 Family Hardware Specifications R70 R80 R81 Table 10-12. JTAG Timing Characteristic IEEE 1149 ...
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... Figure 10-34. JTAG Test Clock Input Timing TCK TMS, TDI TDO Figure 10-35. JTAG Test Access Port Timing Diagram TCK TRST Figure 10-36. JTAG TRST Timing Diagram 42 MPC860 Family Hardware Specifications J82 J83 J82 J85 J86 J87 J88 J91 J90 J83 J84 J89 MOTOROLA ...
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... STBI low to STBO high (Tx interlock) 29 Data-in setup time to clock high 30 Data-in hold time from clock high 31 Clock low to data-out valid (CPU writes data, control, or direction Specification 23. MOTOROLA MPC860 Family Hardware Specifications J92 J93 Table 11-13. PIP/PIO Timing Characteristic CPM Electrical Characteristics J94 J95 ...
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... PIP/PIO AC Electrical Specifications DATA-IN STBI STBO Figure 11-38. PIP Rx (Interlock Mode) Timing Diagram DATA-OUT STBO (Output) STBI (Input) Figure 11-39. PIP Tx (Interlock Mode) Timing Diagram DATA-IN STBI (Input) STBO (Output) Figure 11-40. PIP Rx (Pulse Mode) Timing Diagram 44 MPC860 Family Hardware Specifications MOTOROLA ...
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... Table 11-14 provides the IDMA controller timings as shown in Figure 11-43 through Figure 11-46. Table 11-14. IDMA Controller Timing Num 40 DREQ setup time to clock high 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high MOTOROLA MPC860 Family Hardware Specifications IDMA Controller AC Electrical Specifications Characteristic 26 ...
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... Figure 11-43. IDMA External Requests Timing Diagram CLKO (Output) TS (Output) R/W (Output) DATA TA (Input) SDACK Figure 11-44. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA 46 MPC860 Family Hardware Specifications Characteristic All Frequencies Min Max — 12 — 20 — — MOTOROLA Unit ...
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... TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 11-45. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) DATA TA (Output) SDACK Figure 11-46. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MOTOROLA MPC860 Family Hardware Specifications IDMA Controller AC Electrical Specifications ...
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... TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid 48 MPC860 Family Hardware Specifications Characteristic Table 11-16. Timer Timing Characteristic All Frequencies Min Max — — 51 All Frequencies Min Max 10 — 1 — 2 — 3 — MOTOROLA Unit Unit ns CLK CLK CLK ns ...
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... L1SYNC valid to L1ST(1–4) valid 79 L1CLK edge to L1ST(1–4) invalid 80 L1CLK edge to L1TXD valid 80A L1TSYNC valid to L1TXD valid 81 L1CLK edge to L1TXD high impedance 82 L1RCLK, L1TCLK frequency (DSC =1) MOTOROLA MPC860 Family Hardware Specifications Serial Interface AC Electrical Specifications Table 11-17. SI Timing ...
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... L1RXD (Input) 76 L1ST(4-1) (Output) Figure 11-49. SI Receive Timing Diagram with Normal Clocking (DSC = 0) 50 MPC860 Family Hardware Specifications 71a 72 RFSD BIT0 78 All Frequencies Unit Min Max — — ns — 30.00 ns 1.00 — L1TCL K 42.00 — ns 42.00 — ns — 0. MOTOROLA ...
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... L1RCLK (FE=1, CE=1) (Input) 82 L1RCLK (FE=0, CE=0) (Input) 75 L1RSYNC (Input L1RXD (Input) 76 L1ST(4-1) (Output) L1CLKO (Output) Figure 11-50. SI Receive Timing with Double-Speed Clocking (DSC = 1) MOTOROLA MPC860 Family Hardware Specifications Serial Interface AC Electrical Specifications 72 83a RFSD=1 77 BIT0 ...
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... Serial Interface AC Electrical Specifications L1TCLK (FE=0, CE=0) (Input) 71 L1TCLK (FE=1, CE=1) (Input) 73 L1TSYNC (Input) 80a L1TXD BIT0 (Output) 80 L1ST(4-1) (Output) Figure 11-51. SI Transmit Timing Diagram (DSC = 0) 52 MPC860 Family Hardware Specifications 70 72 TFSD MOTOROLA ...
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... L1RCLK (FE=0, CE=0) (Input) L1RCLK (FE=1, CE=1) (Input) 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 11-52. SI Transmit Timing with Double Speed Clocking (DSC = 1) MOTOROLA MPC860 Family Hardware Specifications Serial Interface AC Electrical Specifications 72 83a 82 TFSD ...
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... Serial Interface AC Electrical Specifications 54 MPC860 Family Hardware Specifications Figure 11-53. IDL Timing MOTOROLA ...
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... The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as an external sync signals. Figure 11-54 through Figure 11-56 show the NMSI timings. MOTOROLA MPC860 Family Hardware Specifications SCC in NMSI Mode Electrical Specifications 1 ...
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... Figure 11-54. SCC NMSI Receive Timing Diagram TCLK1 102 TxD1 (Output) RTS1 (Output) CTS1 (Input) CTS1 (SYNC Input) Figure 11-55. SCC NMSI Transmit Timing Diagram 56 MPC860 Family Hardware Specifications 102 101 100 107 102 101 100 103 105 104 108 107 104 107 MOTOROLA ...
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... TCLK1 clock period 131 TXD1 active delay (from TCLK1 rising edge) 132 TXD1 inactive delay (from TCLK1 rising edge) 133 TENA active delay (from TCLK1 rising edge) MOTOROLA MPC860 Family Hardware Specifications 102 101 100 103 104 107 105 Table 11-20 ...
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... Figure 11-57. Ethernet Collision Timing Diagram RCLK1 RxD1 (Input) RENA(CD1) (Input) Figure 11-58. Ethernet Receive Timing Diagram 58 MPC860 Family Hardware Specifications Characteristic 2 2 120 121 124 125 All Frequencies Unit Min Max — CLK — — 121 123 Last Bit 126 127 MOTOROLA ...
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... Figure 11-59. Ethernet Transmit Timing Diagram RCLK1 RxD1 0 (Input) Start Frame RSTRT (Output) Figure 11-60. CAM Interface Receive Start Timing Diagram REJECT Figure 11-61. CAM Interface REJECT Timing Diagram MOTOROLA MPC860 Family Hardware Specifications 128 121 132 1 1 BIT1 125 137 Ethernet Electrical Specifications ...
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... SPI Master AC Electrical Specifications Table 11-22 provides the SPI master timings as shown in Figure 11-63 and Figure 11-64. 60 MPC860 Family Hardware Specifications Characteristic 151 151 150 NOTE 155 155 All Frequencies Unit Min Max 100 — 50 — 50 — — — 5 — 153 MOTOROLA ...
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... SPIMISO msb (Input) 167 SPIMOSI msb (Output) Figure 11-63. SPI Master ( Timing Diagram MOTOROLA MPC860 Family Hardware Specifications SPI Master AC Electrical Specifications Table 11-22. SPI Master Timing Characteristic 167 166 160 167 166 Data lsb 165 ...
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... MPC860 Family Hardware Specifications 167 166 160 167 166 Data 165 164 Data Table 11-23. SPI Slave Timing Characteristic lsb msb 166 lsb All Frequencies Min Max 2 — 15 — 15 — 1 — 1 — 20 — 20 — — 50 MOTOROLA msb Unit t cyc cyc t cyc ...
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... SPICLK (CI=1) (Input) 177 SPIMISO Undef (Output) 175 SPIMOSI msb (Input) Figure 11-66. SPI Slave ( Timing Diagram MOTOROLA MPC860 Family Hardware Specifications SPI Slave AC Electrical Specifications 172 182 181 170 181 182 180 Data lsb 179 181 182 ...
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... Z All Frequencies Unit Min Max 0 BRGCLK/48 Hz BRGCLK/48 Hz — s — s — s — s — — s — s — 1/(10 * fSCL) s — 1/(33 * fSCL) s — s MOTOROLA ...
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... U4 UTPB, SOC, Rxclav and Txclav hold time U5 UTPB, SOC active delay (and PHREQ and PHSEL active delay in MPHY mode) Figure 12-68 shows signal timings during UTOPIA receive operations. MOTOROLA MPC860 Family Hardware Specifications UTOPIA AC Electrical Specifications 204 207 209 210 ...
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... Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5 3 MPC860 Family Hardware Specifications HighZ at MPHY HighZ at MPHY MOTOROLA ...
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... The transmitter functions correctly MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. Table 13-28 provides information on the MII transmit signal timing. MOTOROLA MPC860 Family Hardware Specifications M3 M4 ...
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... Figure 13-72 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL Figure 13-72. MII Async Inputs Timing Diagram 68 MPC860 Family Hardware Specifications Min 5 — Min 1.5 M9 Max Unit — 65% MII_TX_CLK period 65% MII_TX_CLK period Max Unit — MII_TX_CLK period MOTOROLA ...
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... MII_MDC pulse width low Figure 13-73 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) Figure 13-73. MII Serial Management Channel Timing Diagram MOTOROLA MPC860 Family Hardware Specifications MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Characteristic M14 M10 ...
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... MPC860 Family Hardware Specifications 2 Ethernet Support Multi-Channel 1 SCCs (Mbps) HDLC Support 1 10/100 2 10 10/100 10/100 10/100 10/100 Frequency Temperature (MHz) (Tj) ATM Support yes yes N/A N/A Yes Yes Yes Yes N/A N/A Yes Yes Yes Yes Yes Yes Order Number MOTOROLA ...
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... Table 14-33. MPC860P Package/Frequency Availability Package Type Ball grid array (ZP suffix) Ball grid array (CZP suffix) 1 Where nn specifies version D.3 (as D3) or D.4 (as D4). MOTOROLA MPC860 Family Hardware Specifications Mechanical Data and Ordering Information 50 0° to 95°C XPC860DEZP50nn XPC860DTZP50nn XPC860ENZP50nn ...
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... OP1 MODCK1 K BADDR30 IPB6 ALEA IRQ4 J IPB5 IPB1 IPB2 ALEB H M_COL IRQ2 IPB0 IPB7 G BR IRQ6 IPB4 IPB3 GND F VDDL TS IRQ3 BURST VDDH E CS3 CS6 CS2 GPLA5 BDIP TEA C CS7 CS0 TA GPLA4 B CS5 CE1A WR GPLB4 A WE1 WE3 CS4 CE2A CS1 MOTOROLA ...
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... Mechanical Dimensions of the PBGA Package For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to Motorola Application Note, Plastic Ball Grid Array (order number: AN1231/D), available from your local Motorola sales offi ...
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... B23 max value @ 66 Mhz from 2ns to 8ns, added this revision history table 6 10/2002 Added the MPC855T. Corrected Figure 9-25 on page 36. 6.1 11/2002 Corrected UTOPIA RXenb* and TXenb* timing values. Changed incorrect usage of Vcc to Vdd. Corrected dual port RAM to 8Kbytes. 74 MPC860 Family Hardware Specifications Change MOTOROLA ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC860 Family Hardware Specifications Document Revision History 75 ...
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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. ...