CXP85840A Sony, CXP85840A Datasheet
CXP85840A
Specifications of CXP85840A
Related parts for CXP85840A
CXP85840A Summary of contents
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... CXP85840A/85848A/85856A CMOS 8-bit Single Chip Microcomputer Description The CXP85840A/85848A/85856A are the CMOS 8-bit microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, closed caption decoder, data slicer, on-screen 2 display function bus interface, PWM output, remote control reception circuit, HSYNC counter and watchdog timer, besides the basic configurations of 8-bit CPU, ROM, RAM, I/O ports ...
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... CXP85840A/85848A/85856A ...
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... MP (Pin 49) is always connected to GND. PC3 1 PC2 2 PC1 3 PC0 RST 15 Vss 16 XTAL CVss 25 LFC2 26 LFC1 27 VIN Cap 30 31 PB5 32 – 3 – CXP85840A/85848A/85856A PC4 64 PC5 63 PC6 62 PC7 61 PF0/PWM0 60 PF1/PWM1 59 PF2/PWM2 58 PF3/PWM3 57 PF4/SCL0/PWM4 56 PF5/SCL1/PWM5 55 PF6/SDA0/PWM6 54 53 PF7/SDA1/PWM7 52 PE0/TO PE1 51 PE2/INT0 Vss EXLC 44 XLC ...
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... XTAL 11 EXTAL 12 PA5/AN5 13 PA4/AN4 14 PA3/AN3 15 PA2/AN2 16 PA1/AN1 17 PA0/AN0 18 CVss Note (Pin 40) is always connected Vss (Pins 10 and 42) are both connected to GND (Pin 43) is always connected to GND. – 4 – CXP85840A/85848A/85856A PF3/PWM3 51 PF4/SCL0/PWM4 50 49 PF5/SCL1/PWM5 48 PF6/SDA0/PWM6 47 PF7/SDA1/PWM7 46 PE0/TO 45 PE1 44 PE2/INT0 43 MP Vss EXLC 38 ...
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... PWM output. (8 pins) and large current (12mA) N-channel 2 open drain output bus interface transfer clock I/O. Lower 4 bits are (2 pins) medium drive voltage (12V); upper 4 bits bus interface transfer data I/O. are 5V drive. (2 pins) (8 pins) 6-bit OSD display output. (6 pins) – 5 – CXP85840A/85848A/85856A ...
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... System reset; active at Low level. I/O pin. Outputs a Low level when the power is turned on and the internal power-on reset function operates. (Mask option) Test mode pin. Always connect to GND. No connected. Under normal operation, connect to V Positive power supply. GND. Connect two Vss pins to GND. – 6 – CXP85840A/85848A/85856A . DD ...
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... Port A direction “0” when reset RD (Port A) Schmitt input Ports B, C data Ports B, C direction “0” when reset Data bus RD (Ports B, C) Schmitt input INT1 – 7 – CXP85840A/85848A/85856A When reset Input IP protection circuit Hi-Z IP Hi-Z Input polarity “0” when reset IP ...
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... Circuit format Port D data Port D direction “0” when reset Schmitt input RD (Port D) SCK (Port (Port E) INT0 – 8 – CXP85840A/85848A/85856A When reset IP Large current 12mA IP Schmitt input Large current 12mA PE0, PE1: IP High level PE2: Hi-Z Schmitt input only for PE2 ...
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... Port F function selection Schmitt input “0” when reset 2 C circuit) Writing data to output polarity register brings output to active – 9 – CXP85840A/85848A/85856A When reset 12V drive voltage Large current 12mA IP BUS other I C pins (SCL1 for SCL0) Large current 12mA Oscillation control ...
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... Diagram shows the circuit composition during oscillation. IP • Feedback resistor is removed during stop mode. (This device does not enter the stop mode.) Pull-up resistor OP Mask option Schmitt input From power-on reset circuit (Mask option) – 10 – CXP85840A/85848A/85856A When reset Oscillation Low level ...
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... 0.4 –0.3 V +75 –20 °C – 11 – CXP85840A/85848A/85856A (Vss = 0V reference) Unit Remarks PF0 to PF3 pins mA mA Total of all output pins Ports excluding large current outputs mA (value per pin) Large current output ports mA 2 (value per pin ) mA Total of all output pins ° ...
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... C = 15pF Stop mode V = 5.5V, termination of DD 12MHz oscillation 5. PE, SCL, Clock 1MHz SDA, EXLC, EXTAL, 0V for no-measured pins VIN, RST – 12 – CXP85840A/85848A/85856A (Ta = –20 to +75°C, Vss = 0V reference) Min. Typ. = –0.5mA 4 –1.2mA 3 1.8mA OL = 3.6mA OL = 12.0mA OL = 3.0mA OL = 4.0mA OL = 5.5V 0 ...
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... Fig. 1, Fig. 2 EXTAL , Fig. 1, Fig. 2 EXTAL External clock drive , Fig. 1, Fig. 2 EXTAL External clock drive , EC Fig Fig External clock XTAL EXTAL – 13 – CXP85840A/85848A/85856A = 4.5 to 5.5V, Vss = 0V reference) DD Typ. Min. 12.0 37 sys + – 0. XTAL OPEN 0. Max. ...
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... SCK input mode SO SCK output mode t KCY SIK KSI 0.8V Input data 0.2V t KSO 0.8V DD Output data 0.2V DD – 14 – CXP85840A/85848A/85856A = 4.5 to 5.5V, Vss = 0V reference) DD Min. Max. 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 0. Unit ns ns ...
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... ADC 6 (CKS) of the A/D control register (ADC: 00F9 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FE V FT PCK1 / /16) EX – 15 – CXP85840A/85848A/85856A = 4.5 to 5.5V, Vss = 0V reference) DD Min. Typ. Max. –10 10 4910 4970 5030 ADC 3 160/f ADC 3 12 and vice versa ...
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... Pins Conditions Min. INT0 t IH INT1 t IL INT2 t 32/fc RST RSL RSL 0.2V DD (Ta = –25 to +75°C, Vss = 0V reference) Pins Conditions Power-on reset V DD Repeated power-on reset – 16 – CXP85840A/85848A/85856A Max. Unit 1 µs µ 0.2V DD Min. Max. Unit 0. 0.2V t OFF ...
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... SDA, SCL F t SDA, SCL SU; STO HD; DAT HIGH SU; DAT device device – 17 – CXP85840A/85848A/85856A = 4.5 to 5.5V, Vss = 0V reference) DD Conditions Min. 0 4.7 4.0 4.7 4.0 4 250 4.7 t HD; STA t t SU; STO SU; STA less) can be used to reduce the Max. Unit 100 kHz µs µs µ ...
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... Pins Conditions EXLC f Fig. 12 OSC XLC t HSYNC Fig. 11 HWD t VSYNC Fig. 11 VWD t HSYNC Fig. 11 HCG t VSYNC Fig. 11 VCG t HWD ) h t VCG t VWD 0. 0.2V DD EXLC XLC – 18 – CXP85840A/85848A/85856A Unit Min. Max. 4 16.5 MHz 1.2 µ 200 ns 1.0 µs t HCG 0. ...
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... LFC2 VIN 2.0 5. LFC2 C LPF LFC1 C VIN Cap Ccap CVss – 19 – CXP85840A/85848A/85856A = 4.5 to 5.5V, Vss = 0V reference) DD Unit Remarks The B characteristics or more of µF temperature characteristics is recommended. The B characteristics or more of pF temperature characteristics is recommended. The B characteristics or more of µF temperature characteristics is recommended. Vp-p ...
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... The XTAL series resistor can reduce the effect of the noise caused by the electrostatic discharge. Mask Option Table Item Reset pin pull-up resistor Non-existent Power-on reset circuit Non-existent 2 Model fc (MHz) C (pF 12.0 12.0 15 Content Existent Existent – 20 – CXP85840A/85848A/85856A C (pF Circuit example ( (i) ...
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... Sleep mode Parameter curve for OSD oscillation L vs. C (theoretically calculated value OSC – Capacitance [pF – 21 – CXP85840A/85848A/85856A 25°C, Typical) DD 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode Sleep mode – System clock [MHz] 10MHz 12MHz 14MHz 16MHz 100 16 ...
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... PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SDIP-64P-01 P-SDIP64-17.1x57.6-1.778 LEAD MATERIAL 8.6g PACKAGE MASS ITEM SPEC. ALLOY 42 Sn-Bi 2.5% 5-18 m – 22 – CXP85840A/85848A/85856A 0˚ to 15˚ 0˚ to 15˚ EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY ...
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... PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-64P-L01 P-QFP64-14x20-1.0 LEAD MATERIAL PACKAGE MASS ITEM SPEC. ALLOY 42 Sn-Bi 2.5% 5-18 m – 23 – CXP85840A/85848A/85856A + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.05 ˚ ˚ 0 to10 EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.5g + 0.1 0.15 – ...