K6F8016U6A Samsung, K6F8016U6A Datasheet
K6F8016U6A
Specifications of K6F8016U6A
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K6F8016U6A Summary of contents
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... K6F8016U6A Family Document Title 512K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. History 0.0 Initial draft 0.1 Revise - Change Package type from FBGA to TBGA 1.0 Finalize - Improved I from 4 to 3mA CC1 - Removed 1.01 ...
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... SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The K6F8016U6A families are fabricated by SAMSUNG s advanced full CMOS process technology. The families support industrial operating temperature ranges and have chip scale package for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current ...
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... K6F8016U6A Family PRODUCT LIST Part Name K6F8016U6A-EF55 K6F8016U6A-EF70 FUNCTIONAL DESCRIPTION means don t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition ...
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... K6F8016U6A Family RECOMMENDED DC OPERATING CONDITIONS Item Supply voltage Ground Input high voltage Input low voltage Note =- otherwise specified Overshoot: V +2.0V in case of pulse width 20ns Undershoot: -2.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE 1) (f=1MHz, T =25 C) ...
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... K6F8016U6A Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(see right): C =100pF+1TTL L C =30pF+1TTL L AC CHARACTERISTICS (Vcc=2.7~3.3V, Industrial product: T Parameter List ...
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... K6F8016U6A Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) Address Data Out Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) Address UB Data out High-Z NOTES (READ CYCLE and are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage ...
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... K6F8016U6A Family TIMING WAVEFORM OF WRITE CYCLE(1) Address UB Data in Data Undefined Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address UB Data in Data out (WE Controlled CW( WP(1) t AS( High-Z t WHZ (CS Controlled AS(3) CW( WP( Data Valid High-Z 7 CMOS SRAM t WR( High-Z Data Valid WR( High-Z Revision 3.0 January 2002 ...
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... K6F8016U6A Family TIMING WAVEFORM OF WRITE CYCLE(3) Address UB Data in High-Z Data out NOTES (WRITE CYCLE wri e occurs during the overlap low for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran- sition when CS goes high and WE goes high. The ...
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... K6F8016U6A Family PACKAGE DIMENSION 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View B #A1 Side View D C Min Typ A - 0.75 B 6.90 7. 3.75 C 8.90 9. 5.25 D 0.40 0.45 E 0.80 0. 0.55 E2 0.30 0. Bottom View Detail A Max - Notes. 7.10 1. Ball counts: 48(8 row x 6 column) 2. Ball pitch: (x,y)=(0.75 x 0.75)(typ ...