IDT723643 Integrated Device Technology, Inc., IDT723643 Datasheet
IDT723643
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IDT723643 Summary of contents
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... RAM ARRAY 36 36 256 x 36 512 x 36 1,024 x 36 Write Read Pointer Pointer Status Flag Logic Programmable Flag Timing Offset Registers Mode Mail 2 Register 1 TM IDT723623 IDT723633 IDT723643 MBF1 EF/ FWFT CLKB CSB W/RB Port-B ENB Control MBB Logic BE BM SIZE 3269 drw01 ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data from port A to port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 useful since it permits flushing of the FIFO memory without changing any configuration settings. These devices have two modes of operation: In the IDT Standard mode, the ...
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... FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 16 for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 Symbol Name I/O MBF2 MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 Mail2 Register O ...
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... COMMERCIAL TEMPERATURE RANGE Commercial Unit –0 –0 +0 –0 +0 ±20 mA ±50 mA ±50 mA ±400 mA –65 to 150 ° C IDT723623 IDT723633 IDT723643 Commerical t = 12, 15ns CLK (2) Min. Typ. Max. 2.4 — — — — 0.5 — — ±10 — — ±10 — — 8 — — ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723623/723633/723643 ...
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... Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. COMMERCIAL TEMPERATURE RANGE (2) (2) 8 Commercial IDT723623L12 IDT723623L15 IDT723633L12 IDT723633L15 IDT723643L12 IDT723643L15 Min. Max. Min. Max. Unit — 83 — 66.7 MHz 12 — ...
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... Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. Parameter (2) (3) and CLKB to A0-A35 9 COMMERCIAL TEMPERATURE RANGE Commercial IDT723623L12 IDT723623L15 IDT723633L12 IDT723633L15 IDT723643L12 IDT723643L15 Min. Max. Min. Max. Unit ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 RESET (RS1/RS2) After power up, a Reset operation must be performed by providing a LOW pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the IDT723623/723633/723643 ...
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... 252 for the IDT723623 508 for the IDT723633; and 1 to 1,020 for the IDT723643. After all the offset registers are programmed from Port A the FIFO begins normal operation. — SERIAL LOAD To program the X and Y registers serially, initiate a Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of RS1 ...
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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 can be programmed from 1 to 508 (IDT723623 1,020 (IDT723633 2,044 (IDT723643). When the option to program the offset registers serially is chosen, the Full/ Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/IR is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO operation ...
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... Almost-Empty flag and Almost-Full flag offset programming section). An Almost- Full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) for the IDT723623, IDT723633, or IDT723643 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723623, IDT723633, or IDT723643 respectively ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For an 18-bit bus size, 18 bits of mailbox data are placed on ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 BYTE ORDER ON PORT SIZE BYTE ORDER ON PORT SIZE SIZE ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA CLKB t RSTS (3) RS1/RS2 BE/FWFT SPM FS1,FS0 FF/IR EF/OR t RSF AE t RSF AF t RSF MBF1, MBF2 NOTES: 1. PRS must be HIGH during ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA 1 4 RS1 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FF/IR ENA A0-A35 NOTE: 1. CSA = LOW, W/RA = HIGH, MBA = ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t CLKH t CLKL CLKA FF/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA t DS A0-A35 NOTE: 1. Written to ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB FF/OR HIGH CSB W/RB MBB ENB B0-B17 (Standard Mode) OR B0-B17 (FWFT Mode) NOTE: 1. Unused word B18-B35 are indeterminate. DATA SIZE TABLE FOR WORD READS (1) ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB EF/OR HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode MDV t B0-B8 EN (FWFT Mode) NOTE: 1. Unused bytes ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA LOW CSA W/RA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IR HIGH A0-A35 W1 t SKEW1 CLKB FIFO Empty ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA CSA LOW W/RA HIGH t ENS2 t MBA t ENS2 t ENA FF HIGH A0-A35 W1 t SKEW1 CLKB EF FIFO Empty CSB LOW ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB OR HIGH B0-B35 Previous Word in FIFO Output Register CLKA FIFO Full ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EF HIGH B0-B35 Previous Word in FIFO Output Register CLKA FF FIFO ...
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... FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT723623, 512 for the IDT723633, 1,024 for the IDT723643. ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN FIFO Output Register A0-A35 NOTE: 1. ...
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IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 ...
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IDT X XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. 10/04/2000 pgs. 1 through 28. 03/21/2001 pgs 6 and 7. 08/01/2001 pgs and 28. CORPORATE HEADQUARTERS 2975 Stender Way ...