IDT723631 Integrated Device Technology, Inc., IDT723631 Datasheet

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... Industrial temperature range (- + avail- able, tested to military electrical specifications DESCRIPTION: The IDT723631/723641/723651 is a monolithic high- speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies MHz and has read access times as fast as 12ns. The 512/1024/2048 x 36 dual-port SRAM FIFO AF buffers data from port A to Port B ...

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... Two or more devices may be used in parallel to create wider data paths. Expansion is also possible in word depth. The IDT723631/723641/723651 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PIN CONFIGURATION (CONTINUED GND GND GND Note – No internal connection TQFP (PN120-1, order code: PF) TOP VIEW COMMERCIAL TEMPERATURE RANGE GND GND GND GND 61 3023 drw 03 3 ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PIN DESCRIPTION Symbol Name A0-A35 Port-A Data AE Almost-Empty Flag AF Almost-Full Flag. B0-B35 Port-B Data. CLKA Port-A Clock CLKB Port-B Clock CSA Port-A Chip Select CSB Port-B Chip Select ENA Port-A Enable ENB ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PIN DESCRIPTION (CONTINUED) Symbol Name MBF2 Mail2 Register Flag OR Output-Ready Flag RFM Read From Mark RST Reset RTM Retransmit Mode Port-A Write/Read Select W /RB Port-B Write/Read Select I/O MBF2 O is set LOW by the LOW-to-HIGH transition of CLKB that writes data to MBF2 the mail2 register ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I V (2) Output Voltage Range O I Input Clamp Current Output Clamp Current Continuous Output Current, (V ...

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... Only applies when serial load method is used to program flag offset registers. 3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. IDT723631L15 IDT723631L20 IDT723631L30 IDT723641L15 IDT723641L20 IDT723641L30 IDT723651L15 IDT723651L20 IDT723651L30 Min. – ...

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... LOW to B0-B35 at high impedance NOTES: 1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. IDT723631L15 IDT723631L20 IDT723631L30 IDT723641L15 IDT723641L20 IDT723641L30 IDT723651L15 IDT723651L20 IDT723651L30 Min. ...

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... Each register value can be pro- grammed from 1 to 508 (IDT723631 1020 (IDT723641), and 1 to 2044 (IDT723651). After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM ...

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... SYNCHRONIZED FIFO FLAGS Each IDT723631/723641/723651 FIFO flag is synchro- nized to its port clock through at least two flip-flop stages. This is done to improve the flags’ reliability by reducing the prob- ability of metastable events on their outputs when CLKA and CLKB operate asynchronously to one another ...

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... A, or programmed serially (see almost-empty flag and almost-full flag offset programming). The almost-full flag is LOW when the number of words in the FIFO is greater than or equal to (512-Y), (1024-Y), OR (2048-Y) for the IDT723631, IDT723641, or IDT723651, respectively. The almost-full flag is HIGH when the number of words in the FIFO is less than or equal to [512-(Y+1)], [1024-(Y+1)], or [2048-(Y+1)] for the IDT723631, IDT723641, or IDT723651, respectively ...

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... FIFO is in retransmit mode, but LOW by the write that stores (512 - Y), (1024 - Y), or (2048 - Y) words after the first retransmit word for the IDT723631, IDT723641, or IDT723651, respectively. The IR flag is set LOW by the 512th, 1024th, or 2048th write after the first retransmit word for the IDT723631, IDT723641, or IDT723651, respectively ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA CLKB t RSTS RST FS1,FS0 RSF AE t RSF AF t RSF MBF1 , MBF2 Figure 1. FIFO Reset Loading X and Y with a Preset Value of Eight CLKA 4 RST t t FSS FSH FS1,FS0 IR ENA A0 - A35 NOTE: CSA R 1. ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA 4 RST IR t FSS SEN FS1/ t FSH t FSS FS0/SD NOTE not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH. Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA CSA LOW HIGH t t ENS2 ENH2 MBA t t ENS1 ENH1 ENA HIGH A35 W1 t SKEW1 CLKB Old Data in FIFO1 Output Register OR CSB LOW W HIGH /RB LOW MBB ENB B0 -B35 Old Data in FIFO Output Register NOTE: 1 ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 CLK t t CLKH CLKL CLKB CSB LOW W /RB HIGH MBB LOW t ENS1 ENB HIGH OR B0 -B35 Previous Word in FIFO Output Register CLKA IR FIFO Full CSA LOW R HIGH W A MBA ENA A0 - A35 NOTE: 1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown ...

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... NOTES: 1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for the rising CLKB edge and rising CLKA edge is less than tSKEW2, then 2. Depth is 512 for the IDT723631, 1024 for the IDT723641, and 2048 for the IDT723651. CSA R 3 ...

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... CLKB edge and rising CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown. 2. Depth is 512 for the IDT723631, 1024 for the IDT723641, and 2048 for the IDT723651 the value loaded in the almost-full flag offset register. ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKA t ENS2 CSA MBA ENA A0 - A35 CLKB MBF1 CSB W /RB MBB ENB B35 FIFO Output Register t ENH2 PMF t MDV t PMR W1 (Remains valid in Mail1 Register after read) Figure 14. Timing for Mail1 Register and ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 CLKB t ENS2 CSB W /RB MBB ENB B0 - B35 CLKA MBF2 CSA MBA ENA A35 t ENH2 PMF t PMR W1 (Remains valid in Mail2 Register after read) Mail2 Mail2 Figure 15. Timing for Register and COMMERCIAL TEMPERATURE RANGE ...

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... TTL HIGH level of 3 output capacitance load switching frequency of an output O When no reads or writes are occurring on the IDT723631/723641/723651, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by 0.209 mA/MHz TYPICAL CHARACTERISTICS SUPPLY CURRENT ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input t S Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PLZ Low-Level Output t PZH High-Level Output t PHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE: 1 ...

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... IDT723631/723641/723651 CMOS SyncFIFO 512 x 36, 1024 x 36, 2048 x 36 ORDERING INFORMATION IDT XXXXXX X Device Type Power Speed Package Process/ Temperature Range COMMERCIAL TEMPERATURE RANGE BLANK Commercial ( + Thin Quad Flat Pack (TQFP, PN120-1) PQF Plastic Quad Flat Pack (PQFP, PQ132-1) 15 Commercial Only ...