IDT723612 Integrated Device Technology, Inc., IDT723612 Datasheet
IDT723612
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IDT723612 Summary of contents
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... Industrial temperature range (-40oC to +85oC) is avail- able, tested to military electrical specifications DESCRIPTION: The IDT723612 is a monolithic high-speed, low-power BiCMOS bi-directional clocked FIFO memory. It supports clock frequencies MHz and has read access times as Port-A ...
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... The empty flag ( AEA AEB ( , ) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723612 is characterized for operation from PQFP (PQ132-1, order code: PQF) TOP VIEW COMMERCIAL TEMPERATURE RANGE FFB ...
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... IDT723612 BiCMOS SyncBiFIFO PIN CONFIGURATIONS (CONT GND GND GND Note internal connection TQFP (PN120-1, order code: PF) TOP VIEW COMMERCIAL TEMPERATURE RANGE GND GND GND 3136 drw 03 3 ...
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... IDT723612 BiCMOS SyncBiFIFO PIN DESCRIPTION Symbol Name A0-A35 Port-A Data AEA Almost-Empty Flag (Port A) AEB Port-B Almost-Empty Flag (PortB) AFA Port-A Almost-Full Flag (Port A) AFB Port-B Almost-Empty Flag (Port B) B0-B35 Port-B Data. CLKA Port-A Clock CLKB Port-B Clock CSA Port-A Chip Select ...
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... IDT723612 BiCMOS SyncBiFIFO PIN DESCRIPTION (CONTINUED) SYMBOL NAME MBB Port-B Mailbox Select MBF1 Mail1 Register Flag MBF2 Mail2 Register Flag ODD/ Odd/Even Parity EVEN Select PEFA Port-A Parity Error Flag (Port A) Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the ...
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... IDT723612 BiCMOS SyncBiFIFO ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I (2) V Output Voltage Range O I Input Clamp Current Output Clamp Current Continuous Output Current, (V OUT I Continuous Current Through V CC ...
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... Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relation- ship between CLKA cycle and CLKB cycle. IDT723612L15 IDT723612L20 IDT723612L30 Min. – ...
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... Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 3. Only applies when reading data from a mail register. = 30pF L IDT723612L15 IDT723612L20 IDT723612L30 Min. 2 FFA and 2 EFA ...
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... IDT723612 BiCMOS SyncBiFIFO SIGNAL DESCRIPTIONS RESET The IDT723612 is reset by taking the reset ( LOW for at least four port-A clock (CLKA) and four port-B clock (CLKB) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the ...
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... IDT723612 BiCMOS SyncBiFIFO CSB transition of CLKB when is LOW, W/ EFB HIGH, MBB is LOW, and is HIGH (see Table 3). The setup and hold time constraints to the port clocks for CSA CSB the port chip selects ( , ) and write/read selects ( are only for enabling write and read operations and are not related to high-impedance control of the data outputs ...
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... B0-B35 inputs. PARITY GENERATION A HIGH level on the port-A parity generate select (PGA) or port-B parity generate select (PGB) enables the IDT723612 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-A8, A9-A17, A18- 26, and A27-A35, with the most significant bit of each byte used as the parity bit ...
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... IDT723612 BiCMOS SyncBiFIFO inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ The generated parity bits are substituted for the levels origi- nally written to the most significant bits of each byte as the word is read to the data outputs ...
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... IDT723612 BiCMOS SyncBiFIFO CLKA CLKB t RSTS RST FS1,FS0 FFA EFA FFB EFB AEA AFA MBF1 t RSF , MBF2 AEB AFB Figure 1. Device Reset Loading the X Register with the Value of Eight t RSTH t FSS 0,1 t WFF t REF t WFF t REF t PAE t PAF t PAE t PAF COMMERCIAL TEMPERATURE RANGE ...
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... IDT723612 BiCMOS SyncBiFIFO CLK t CLKH t CLKL CLKA FFA HIGH t ENS1 CSA t ENS1 ENS3 MBA t ENS2 ENA A35 ODD/ EVEN PEFA Note: 1. Written to FIFO1 t ENH1 t ENH1 t ENH3 t ENH2 t ENS2 t DH (1) ( PDPE Valid Figure 2. Port-A Write Cycle Timing for FIFO1 COMMERCIAL TEMPERATURE RANGE ...
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... IDT723612 BiCMOS SyncBiFIFO CLK t t CLKH CLKL CLKB FFB HIGH t ENS1 CSB t ENS1 ENS3 MBB t ENS2 ENB B35 ODD/ EVEN PEFB Note: 1. Written to FIFO2 t ENH1 t ENH1 t ENH3 t ENH2 t ENS2 t DH (1) ( PDPE Valid Figure 3. Port-B Write Cycle Timing for FIFO2 COMMERCIAL TEMPERATURE RANGE ...
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... IDT723612 BiCMOS SyncBiFIFO CLK t t CLKH CLKL CLKB EFB HIGH CSB MBB ENB t MDV B35 t PGS PGB, ODD/ EVEN Note: 1. Read from FIFO1 t CLK t t CLKH CLKL CLKA EFA HIGH CSA MBA ENA t MDV A35 t PGS PGA, ODD/ EVEN Note: 1. Read from FIFO2 ...
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... IDT723612 BiCMOS SyncBiFIFO CLKA CSA LOW HIGH t ENS3 MBA t ENS2 ENA FFA HIGH A35 W1 t SKEW1 CLKB EFB FIFO1 Empty CSB LOW R LOW W/ B LOW MBB ENB B0 -B35 Note the minimum time between a rising CLKA edge and a rising CLKB edge for SKEW1 next CLKB cycle ...
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... IDT723612 BiCMOS SyncBiFIFO CLKB CSB LOW HIGH t ENS3 MBB t ENS2 ENB FFB HIGH B35 W1 t SKEW1 CLKA EFA FIFO2 Empty CSA LOW R LOW W/ A LOW MBA ENA A0 -A35 Note the minimum time between a rising CLKB edge and a rising CLKA edge for SKEW1 next CLKA cycle ...
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... IDT723612 BiCMOS SyncBiFIFO CLK t t CLKH CLKL CLKB CSB LOW R LOW W/ B MBB LOW t ENS2 ENB EFB HIGH B0 - B35 Previous Word in FIFO1 Output Register CLKA FFA FIFO1 Full CSA LOW R HIGH W A MBA ENA A0 - A35 Note the minimum time between a rising CLKB edge and a rising CLKA edge for SKEW1 next CLKA cycle ...
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... IDT723612 BiCMOS SyncBiFIFO CLK t t CLKH CLKL CLKA CSA LOW R LOW W/ A MBA LOW t ENS2 ENA EFA HIGH A0 - A35 Previous Word in FIFO2 Output Register CLKB FFB FIFO2 Full CSB LOW R HIGH W B MBB ENB B0 - B35 Note the minimum time between a rising CLKA edge and a rising CLKB edge for SKEW1 next CLKB cycle ...
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... IDT723612 BiCMOS SyncBiFIFO CLKA t t ENS2 ENA t CLKB AEB X Word in FIFO1 ENB Notes the minimum time between a rising CLKA edge and a rising CLKB edge for SKEW2 next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than t transition HIGH one CLKB cycle later than shown ...
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... IDT723612 BiCMOS SyncBiFIFO CLKA t ENS2 ENA AFA [64-(X+1)] Words in FIFO1 CLKB ENB Notes the minimum time between a rising CLKA edge and a rising CLKB edge for SKEW2 next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than t transition HIGH one CLKB cycle later than shown ...
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... IDT723612 BiCMOS SyncBiFIFO CLKA t ENS1 CSA MBA ENA A0 - A35 CLKB MBF1 CSB MBB ENB B35 FIFO1 Output Register Note: 1. Port-B parity generation off (PGB = LOW) Figure 14. Timing for Mail1 Register and t ENH1 PMF t MDV t PMR W1 (Remains valid in Mail1 Register after read) ...
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... IDT723612 BiCMOS SyncBiFIFO CLKB CSB MBB ENB B0 - B35 CLKA MBF2 CSA MBA ENA A35 FIFO2 Output Register Note: 1. Port-A parity generation off (PGA = LOW) Figure 15. Timing for Mail2 Register and t ENH1 t ENS1 PMF t MDV t PMR W1 (Remains valid in Mail2 Register after read) ...
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... IDT723612 BiCMOS SyncBiFIFO ODD/ EVEN MBA PGA t PEFA Valid Note: CSA 1. ENA is HIGH, and is LOW Figure 16. ODD/ ODD/ EVEN MBB PGB t PEFB Valid Note: CSB 1. ENB is HIGH, and is LOW Figure 17. ODD/ t POPE POPE Valid Valid EVEN EVEN MBA, and PGA to t POPE ...
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... IDT723612 BiCMOS SyncBiFIFO ODD/ EVEN CSA LOW MBA PGA t EN A8, A17, A26, A35 Note: 1. ENA is HIGH Figure 18. Parity Generation Timing when Reading from Mail2 Register ODD/ EVEN CSB LOW MBB PGB t EN B8, B17, B26, B35 Note: 1. ENB is HIGH Figure 19. Parity Generation Timing when Reading from Mail1 Register ...
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... switching frequency of an output output HIGH level voltage output LOW level voltage OL When no reads or writes are occurring on the IDT723612, the power dissipated by a single clock (CLKA or CLKB) input running at frequency f is calculated by 0.290 mA/MHz TYPICAL CHARACTERISTICS SUPPLY CURRENT vs ...
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... IDT723612 BiCMOS SyncBiFIFO PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t PLZ Low-Level Output t PZH High-Level Output t PHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Note: 1. Includes probe and jig capacitance ...
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... IDT723612 BiCMOS SyncBiFIFO ORDERING INFORMATION IDT XXXXXX X XX Device Type Power Speed X X Package Process/ Temperature Range BLANK PF PQF 723612 COMMERCIAL TEMPERATURE RANGE Commercial ( +70 C) Thin Quad Flat Pack (TQFP, PN120-1) Plastic Quad Flat Pack (PQFP, PQ132-1) Commercial Only Clock Cycle Time (t ...