IDT72235 Integrated Device Technology, Inc., IDT72235 Datasheet

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IDT72235

Manufacturer Part Number
IDT72235
Description
CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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FEATURES:
• 256 x 18-bit organization array (72205LB)
• 512 x 18-bit organization array (72215LB)
• 1024 x 18-bit organization array (72225LB)
• 2048 x 18-bit organization array (72235LB)
• 4096 x 18-bit organization array (72245LB)
• 15 ns read/write cycle time
• Easily expandable in depth and width
• Read and write clocks can be asynchronous or coincident
• Dual-Port zero fall-through time architecture
• Programmable almost-empty and almost-full flags
• Empty and Full flags signal FIFO status
• Half-Full flag capability in a single device configuration
• Output enable puts output data bus in high-impedance
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP),
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40
DESCRIPTION:
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such
FUNCTIONAL BLOCK DIAGRAM
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1996 Integrated Device Technology, Inc.
state
pin grid array (PGA), and plastic leaded chip carrier
(PLCC)
able, tested to military electrical specifications
Integrated Device Technology, Inc.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
(
HF
)/
WXO
RXO
WXI
RXI
RS
FL
EXPANSION LOGIC
WRITE CONTROL
WRITE POINTER
WEN
RESET LOGIC
LOGIC
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
WCLK
O
C to +85
CMOS SyncFIFO
256 x 18, 512 x 18, 1024 x 18, 2048 x
18 and 4096 x 18
O
C) is avail-
OE
OUTPUT REGISTER
1024 x 18, 2048 x 18
256 x 18, 512 x 18
INPUT REGISTER
RAM ARRAY
4096 x 18
Q0-Q17
5.16
D0-D17
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
port is controlled by a free-running clock (WCLK), and a data
input enable pin (
FIFO on every clock when
is controlled by another clock pin (RCLK) and another enable
pin (
single clock operation or the two clocks can run asynchronous
of one another for dual-clock operation. An Output Enable pin
(
output.
and Full (
(
grammable flags is controlled by a simple state machine, and
is initiated by asserting the Load pin (
is available when the FIFO is used in a single device configu-
ration.
are depth expandable using a daisy-chain technique. The XI
and
sion configuration, FL is grounded on the first device and set
to HIGH for all other devices in the daisy chain.
fabricated using IDT’s high-speed submicron CMOS technol-
ogy. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B.
OE
PAE
• •
Both FIFOs have 18-bit input and output ports. The input
The synchronous FIFOs have two fixed flags, Empty (
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is
) is provided on the read port for three-state control of the
XO
REN
) and Almost-Full (
pins are used to expand the FIFOs. In depth expan-
). The read clock can be tied to the write clock for
FF
), and two programmable flags, Almost-Empty
WEN
OFFSET REGISTER
READ CONTROL
READ POINTER
). Data is read into the synchronous
RCLK
PAF
WEN
LOGIC
LOGIC
FLAG
). The offset loading of the pro-
REN
is asserted. The output port
LD
LD
). A Half-Full flag (
DECEMBER 1996
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
2766 drw 01
PAE
HF
FF
PAF
EF
/(
WXO
DSC-2766/7
)
HF
1
EF
)
)

Related parts for IDT72235

IDT72235 Summary of contents

Page 1

... OUTPUT REGISTER OE Q0-Q17 5.16 IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB WEN ). Data is read into the synchronous WEN is asserted. The output port ). The read clock can be tied to the write clock for FF ), and two programmable flags, Almost-Empty PAF ) ...

Page 2

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 PIN CONFIGURATIONS 11 10 GND GND GND ...

Page 3

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 PIN CONFIGURATIONS PIN ...

Page 4

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 PIN DESCRIPTION Symbol Name D0–D17 Data Inputs RS Reset WCLK Write Clock WEN Write Enable RCLK Read Clock REN Read Enable ...

Page 5

... IDT72235LB IDT72245LB Military t = 25, 35, 50ns CLK Typ. Max. Min. Typ. Max. — 1 –10 — 10 — 10 –10 — 10 — — 2.4 — ...

Page 6

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 CAPACITANCE ( 1.0MHz) A (1) Symbol Parameter Conditions (2) C Input VIN = 0V IN Capacitance ...

Page 7

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load SIGNAL DESCRIPTIONS: INPUTS: ...

Page 8

... Reset ( ), the Full Flag ( after 256 writes for the IDT72205LB, 512 writes for the IDT72215LB, 1024 writes for the IDT72225LB, 2048 writes for the IDT72235LB and 4096 writes for the IDT72245LB. FF The Full Flag ( ) is updated on the LOW-to-HIGH transi- tion of the write clock (WCLK). ...

Page 9

... IDT72205LB, (512-m) writes for the IDT72215LB, (1024-m) writes for the IDT72225LB, (2048–m) writes for the IDT72235LB and (4096–m) writes for the IDT72245LB. The offset “m” is defined in the FULL offset register. ...

Page 10

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 CLKH WCLK WEN t FF (1) t SKEW1 RCLK REN NOTE: 1. tSKEW1 is the ...

Page 11

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 RCLK t t ENH ENS REN WCLK WEN NOTE the minimum ...

Page 12

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 WCLK (first valid write ENS WEN RCLK EF REN Q - ...

Page 13

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 WRITE WCLK t SKEW1 WEN RCLK t ENH t ENS REN OE LOW t ...

Page 14

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 WCLK t DS DATA WRITE ENS ENH WEN t SKEW2 RCLK EF REN ...

Page 15

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 CLK t CLKH WCLK t ENS LD t ENS WEN – PAE OFFSET t CLK ...

Page 16

... IDT72225B, 2048 – for the IDT72235B and 4096 – for the IDT72245B. 2. 256 - m words in IDT72205B, 512 - m words in IDT72215B, 1024 - m words in IDT72225B, 2048 – m words in IDT72235B and 4096 – m words in IDT72245B. 3. 256 - words in IDT72205B, 512 - words in IDT72215B, 1024 - words in IDT72225B, 2048 – words in IDT72235B and 4096 – words in IDT72245B. ...

Page 17

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 CLKH WCLK WEN HF Half Full or Less RCLK REN WCLK WXO t ENS WEN NOTE: 1. Write to Last ...

Page 18

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 WXI WCLK RXI RCLK OPERATING CONFIGURATIONS SINGLE DEVICE CONFIGURATION A single IDT72205LB/72215LB/72225LB/72235LB/ 72245LB may be used when the application requirements are ...

Page 19

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 WIDTH EXPANSION CONFIGURATION Word width may be increased simply by connecting to- gether the control signals of multiple devices. Status flags ...

Page 20

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 • • • • DATA IN • WRITE CLOCK • WRITE ENABLE • RESET • LOAD FF PAF Figure 22. Block ...

Page 21

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO 256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18 ORDERING INFORMATION IDT XXXXX X Device Type Power Speed Package Process / Temperature Range 5.16 MILITARY AND COMMERCIAL ...

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