IDT72205 Integrated Device Technology, Inc., IDT72205 Datasheet
IDT72205
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IDT72205 Summary of contents
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Integrated Device Technology, Inc. FEATURES: • 256 x 18-bit organization array (IDT72205LB) • 512 x 18-bit organization array (IDT72215LB) • 1,024 x 18-bit organization array (IDT72225LB) • 2,048 x 18-bit organization array (IDT72235LB) • ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 PIN CONFIGURATIONS V GND PIN PLCC (J68-1, order code: J) TOP VIEW TQFP (PN64-1, order code: PF) STQFP (PP64-1, order code: TF) TOP VIEW Commercial And Industrial Temperature Ranges V CC ...
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... O When is LOW, the FIFO is almost full based on the offset programmed into the FIFO. The default offset at reset is 31 from full for IDT72205LB, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/72245LB the single device or width expansion configuration, the device is more than half full ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 ELECTRICAL CHARACTERISTICS (Commercial 10 +70 C; Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 SIGNAL DESCRIPTIONS: INPUTS: DATA Data inputs for 18-bit wide data. CONTROLS RESET ( ) Reset is accomplished whenever the Reset ( taken to a LOW state. During reset, both internal read and write pointers are set to the first location ...
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... NOTES Empty Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127 Full Offset (Default Values : IDT72205 n=31, IDT72215 n = 63, IDT72225/72235/72245 n = 127) EMPTY FLAG ( is HIGH, the WCLK input When the FIFO is empty, read operations. When The EF is updated on the LOW-to-HIGH transition of the REN read clock (RCLK) ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 After half of the memory is filled, and at the LOW-to-HIGH transition of the next write cycle, the Half-Full Flag goes LOW and will remain set until the difference between the write pointer and read pointer is less than or equal to one half of the total memory of the device ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WCLK SKEW1 RCLK NOTES the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that SKEW1 time between the rising edge of RCLK and the rising edge of WCLK is less than t ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK (first valid write ENS RCLK NOTES: 1. When t minimum specification, t SKEW2 FRL 2 The Latency Timing applies only at the Empty Boundary ( CLK SKEW2 or CLK SKEW2 2. The first word is available the cycle after Figure 7 ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t DS DATA WRITE ENS t ENH t t SKEW2 RCLK LOW DATA IN OUTPUT REGISTER 0 17 NOTE: 1. When t minimum specification, t SKEW2 FRL The Latency Timing apply only at the Empty Boundary ( ...
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... D = maximum FIFO Depth. Number of data words written into FIFO memory = 256 - for the IDT72205, 512 - for the IDT72215, 1,024 - for the IDT72225, 2,048 - for the IDT72235 and 4,096 - for the IDT72245. 2. 256 - m words in IDT72205, 512 - m words in IDT72215, 1,024 - m words in IDT72225, 2,048 - m words in IDT72235 and 4,096 - m words in IDT72245. WCLK ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK t ENS NOTE: 1. Write to Last Physical Location. RCLK t ENS NOTE: 1. Read from Last Physical Location. WCLK RCLK t CLKH Note Figure 15. Write Expansion Out Timing t CLKH Note 1 ...
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... WRITE EXPANSION IN ( user must create composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 20 demonstrates a 36-word width by using two IDT72205B/72215B/ 72225B/72235B/72245Bs. Any word width can be attained by adding additional IDT72205B/72215B/72225B/72235B/ 72245Bs. Please see the Application Note AN-83. ...
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... DEPTH EXPANSION CONFIGURATION (WITH PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requir- ing more than 256/512/1,024/2,048/4,096 words of buffering. Figure 21 shows Depth Expansion using three IDT72205LB/ 72215LB/72225LB/72235LB/72245LBs. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the ...
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... IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available as standard product for the 15ns and the 25 ns speed grade Package Process / ...