IDT71V35761 Integrated Device Technology, Inc., IDT71V35761 Datasheet
IDT71V35761
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IDT71V35761 Summary of contents
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... Burst Counter, Single Cycle Deselect The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle ...
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... Ground. N/A NC pins are not electrically connected to the device. HIGH Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V35761/781 to its lowest p ower consumption level. Data retention is guaranteed in Sleep Mode. 6.42 2 Description . If BWE is LOW at the ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect LBO ADV CLK ADSC ADSP 16/17 GW BWE Powerdown OE 36/18 I/O — I I/O — I Commercial and Industrial Temperature Ranges Burst CEN Sequence 2 Burst ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Rating (2) V Terminal Voltage with TERM Respect to GND (3,6) V Terminal Voltage with TERM Respect to GND (4,6) V Terminal Voltage with TERM Respect to GND ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 100 DDQ DDQ DDQ I DDQ NOTES: 1. Pin 14 can either be directly connected Pins 38 and 39 can be either NC or connected ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DDQ I I DDQ DDQ DDQ NOTES: 1. Pin 14 can either be directly connected Pins 38 and 39 can be either NC or connected Pin 64 can be left unconnected and the device will always remain in active mode. ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect DDQ I I DDQ DDQ DDQ I I DDQ DDQ I DDQ I DDQ I DDQ I DDQ NOTES can either be directly connected connected to an input voltage DD 2 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect ( I DDQ D I/O I DDQ E I/O I DDQ F I/O I DDQ G I/O I DDQ (1) ( I/O I DDQ K I/O I DDQ L I/O I DDQ M I/O I DDQ N I DDQ ( LBO ( ( DDQ D NC ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current |I | LZZ |I | Output Leakage Current LO V Output Low Voltage OL V Output High Voltage ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Operation Address Used cte d Cycle , cte d Cycle , cte d Cycle , cte d Cycle , cte d Cycle , Cycle , urst Exte rnal Re ad Cycle , urst Exte rnal ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect GW Operation Read H Read H Write all Bytes L Write all Bytes H (3) Write Byte 1 H (3) Write Byte 2 H (3) Write Byte 3 H (3) Write Byte 4 H NOTES: 1 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Symbol Parameter t Clock Cycle Time CYC (1) Clock High Pulse Width t CH (1) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 13 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges , 6.42 14 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6. ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect CLK ADSP ADSC ADDRESS GW, BWE, BWx CE DATA OUT NOTES input is LOW, ADV is HIGH and LBO is Don't Care for this cycle. 2. (Ax) represents the data for address Ax, etc. ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 19 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 20 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 21 ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect IDT XXX Device Power Speed Package Type X Process/ Temperature Range Blank Commercial (0°C to +70°C) I Industrial (-40°C to +85°C) PF 100-pin Plastic Thin Quad Flatpack (TQFP) ...
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... IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with 3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect 12/31/99 Pg 11, 19 04/04/00 Pg. 18 Pg. 4 06/01/00 Pg. 20 07/15/00 Pg. 7 Pg. 8 Pg. 20 10/25/00 Pg. 8 04/22/03 Pg.4 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc ...