IDT70V3389 Integrated Device Technology, Inc., IDT70V3389 Datasheet
IDT70V3389
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IDT70V3389 Summary of contents
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... Available in a 128-pin Thin Quad Plastic Flatpack (TQFP), 208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid Array Dout0-8_L Dout0-8_R Dout9-17_L Dout9-17_R 64K x 18 MEMORY ARRAY Din_L Din_R ADDR_L ADDR_R 1 IDT70V3389S I/O - I/O 0R 17R CLK R A 15R Counter Address CNTRST R Reg. ADS R CNTEN ...
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... The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V3389 has been optimized for applications having unidirectional or bidirectional data flow ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM I I I/O I 10R 10L DDQL I/O NC I/O V 11L 11R DDQL I/O DDQR 12L I/O 12R DDQR I/O I/O I/O V 13L 14R 13R DDQL I/O V DDQL 14L I/O V I/O NC 15R DDQR 15L M1 M2 ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM A 14L A 15L DDQL 10L IO 10R V DDQR 11L IO 11R IO 12L IO 12R 13R IO 13L IO 14R IO 14L IO 15R IO 15L V DDQL 16R IO 16L V DDQR 17R IO 17L 15R A 14R NOTES: 1. All V pins must be connected to 3.3V power supply. ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Left Port Right Port Chip Enables , , R/W R/W Read/Write Enable Output Enable Address 0L 15L 0R 15R I/O - I/O I/O - I/O Data Input/Output 0L 17L 0R 17R CLK CLK Clock L R ADS ADS Address Strobe Enable ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Previous Addr Address Address Used CLK NOTES: 1. "H" "L" "X" = Don't Care. IH, IL, 2. Read and write operations are controlled by the appropriate setting of R/ Outputs are in Pipelined mode: the data out will be delayed by one cycle. ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter Conditions C Input Capacitance V IN (3) C Output Capacitance V OUT NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from from ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Sym bol Param eter CE and CE I Dynam ic Ope rating DD L Current (Bo th Outputs Disab led , (1) P orts A ctive ) MAX tand by Current SB1 L (1) ( orts - TTL MAX Inp uts ) tand by Current SB2 = V "A" ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50 DATA OUT Figure 1. AC Output Test load tCD (Typical, ns) ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM Symbol Parameter t Clock Cycle Time (Pipelined) CYC2 t Clock High Time (Pipelined) CH2 t Clock Low Time (Pipelined) CL2 t Clock Rise Time R t Clock Fall Time F t Address Setup Time SA t Address Hold Time ...
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... HC CE 0(B1) DATA OUT(B1 ADDRESS (B2) CE 0(B2 DATA OUT(B2) NOTES Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3389 for this waveform, and are setup for depth expansion in this example. ADDRESS 2. UB, LB, OE, and ADS = 1(B1) 1(B2) t CL2 ( CD2 Qn (1) ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM CLK R ADDRESS L MATCH DATA VALID INL t CO CLK R R ADDRESS R MATCH DATA OUTR NOTES UB, LB, and ADS = V , CNTEN, and CNTRST = for the Right Port, which is being read from < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK UB (3) An ADDRESS DATA IN (1) DATA OUT OE READ NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals UB, LB, and ADS = V , CNTEN, and CNTRST = Addresses do not have to be accessed sequentially since ADS = V only ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL (7) An ADDRESS t t SAD HAD ADS CNTEN DATA IN WRITE EXTERNAL ADDRESS t CYC2 t t CH2 CL2 CLK ADDRESS (3) INTERNAL Ax ADDRESS ADS t SAD CNTEN t SCN t t SRST ...
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... Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT70V3389 can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM IDT XXXXX A 99 Device Power Speed Type A A Package Process/ Temperature Range Blank I BF PRF 70V3389 1Mbit (64K x 18-Bit) Synchronous Dual-Port RAM 6.42 16 Industrial and Commercial Temperature Ranges Commercial (0°C to +70°C) Industrial (-40° ...
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... IDT70V3389S High-Speed 64K x 18 Dual-Port Synchronous Pipelined Static RAM 1/18/99: Initial Public Release 3/15/99: Page 9 Additional notes 4/28/99: Added fpBGA paclage 6/8/99: Page 2 Changed package body height from 1.5mm to 1.4mm 6/15/99: Page 5 Deleted note 6 for Table II 7/14/99: Page 2 Corrected pin 8/4/99: ...