IDT7015 Integrated Device Technology, Inc., IDT7015 Datasheet
IDT7015
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IDT7015 Summary of contents
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... Commercial: 12/15/17/20/25/35ns (max.) Low-power operation – IDT7015S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7015L Active: 750mW (typ.) Standby: 1mW (typ.) IDT7015 easily expands data bus width to 18 bits or more using the Master/Slave select when cascading more than one device R/W ...
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... High-Speed Dual-Port Static RAM DESCRIPTION: The IDT7015 is a high-speed Dual-Port Static RAM. The IDT7015 is designed to be used as a stand-alone Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 18-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 18- bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic ...
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... PGA 06 N/C N/C Top View ( SEM R I GND I/O I/O I I/O I/O I INDEX 6. BUSY INT M GND BUSY 11R A IDT7015G 10R G68-1 ( GND A 12R 24 25 N/C N SEM R GND V I/O I I/O I I/O I/O I/O I/O I 2954 drw 04 R ...
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... IDT7015S/L High-Speed Dual-Port Static RAM (1) Inputs CE OE SEM R NOTE: 1. Condition: A — — 12L 0R 12R (1) Inputs CE OE SEM R NOTE: 1. There are eight semaphore flags written to via I/O Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature ...
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... IDT7015S/L High-Speed Dual-Port Static RAM Symbol Parameter Conditions C Input Capacitance IN C Output Capacitance V OUT NOTES: 1. This parameter is determined by device characteristics but is not production tested. 2. 3dV references the interpolated capacitance when the input and output signals switch from from Symbol Parameter ( Input Leakage Current ...
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... IDT7015S/L High-Speed Dual-Port Static RAM Symbol Parameter Dynamic Op e rating Curre nt CC SEM = rts A ctive ) tand b y Curre nt SB1 SEM ( rts - TTL Inp uts tand b y Curre nt SB2 (One P ort - TTL Inp uts) Outp uts Disab SEM rts CE I Full S tandb y Curre nt (B oth ...
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... IDT7015S/L High-Speed Dual-Port Static RAM Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change OH (1,2) t Output Low-Z Time LZ (1,2) t Output High-Z Time HZ t Chip Enable to Power Up Time ...
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... IDT7015S/L High-Speed Dual-Port Static RAM ADDR CE OE R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is de-asserted first OE delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY BDD has no relation to valid output data ...
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... IDT7015S/L High-Speed Dual-Port Static RAM Sym bol Param eter WRITE CYCLE t Write Cy cle Tim Chip E nab f-Write Valid to End -o f-Write AW ( t-up Tim Write Puls Write Tim Data Valid f-Write DW (1,2) t Outp ut Hig h-Z Tim e HZ (4) t Data Ho ld Tim rite Enab le to Outp ut in Hig h-Z ...
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... IDT7015S/L High-Speed Dual-Port Static RAM ADDRESS OE ( SEM ( R DATA OUT DATA IN ADDRESS ( SEM ( R/W DATA IN NOTES must be HIGH during all address transitions write occurs during the overlap ( measured from the earlier R/W (or SEM or R/W) going HIGH to the end of write cycle During this period, the I/O pins are in the output state and input signals must not be applied. ...
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... IDT7015S/L High-Speed Dual-Port Static RAM A -A VALID ADDRESS SEM I R/W OE NOTES for the duration of the above timing (both write and read cycle “DATA VALID” represents all I/O's (I/O -I/O OUT 0 A 0"A" (2) SIDE "A" R/W SEM A 0"B" (2) SIDE R/W "B" ...
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... IDT7015S/L High-Speed Dual-Port Static RAM Sym bol Param eter BUSY TIMING (M BUSY A cce ss Tim e fro BAA BUSY Dis ab le Tim e fro BDA BUSY Tim e fro m Chip E nab le t BAC BUSY Dis ab le Tim e fro m Chip E nab le t BDC itratio n P rio rity S e t-up Tim e ...
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... IDT7015S/L High-Speed Dual-Port Static RAM ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins for the reading port. IL (SLAVE), BUSY is an input. Then for this example, BUSY 4 ...
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... IDT7015S/L High-Speed Dual-Port Static RAM BUSY ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" BUSY S ADDR "A" (2) t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... IDT7015S/L High-Speed Dual-Port Static RAM ADDR "A" ( "A" R/W "A" INT "B" ADDR "B" "B" OE "B" t INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. ...
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... Right Port Writes "1" to Semaphore Left Port Writes "0" to Semaphore Left Port Writes "1" to Semaphore NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7015. 2. There are eight semaphore flags written to via I SEM = V to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. ...
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... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master use the BUSY signal as a write inhibit signal. Thus on the IDT7015 RAM the BUSY pin is an output if the part is used as a master (M/S pin = H), and the BUSY pin is an input if the part used as a slave (M/S pin = L) as shown in Figure 3 ...
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... Perhaps the simplest application of semaphores is their application as resource markers for the IDT7015’s Dual-Port RAM. Say the RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could be used ...
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... When the update is completed, the data structure block is released. This allows the interpreting processor to come back and read the complete data structure, thereby guaranteeing a consistent data structure. SEMAPHORE SEMAPHORE REQUEST FLIP FLOP READ Figure 4. IDT7015 Semaphore Logic 6. PORT WRITE SEMAPHORE READ ...
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... IDT7015S/L High-Speed Dual-Port Static RAM IDT XXXXX A 999 Device Power Speed Package Type NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 1/11/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations ...